\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go and Busy Status\nDuring the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically.\nNote: All registers should be set before writing 1 to this GO_BUSY bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop data transfer if SPI is transferring
#1 : 1
In Master mode, start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive At Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched at the rising edge of SPICLK
#1 : 1
Received data input signal is latched at the falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit At Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed at the rising edge of SPICLK
#1 : 1
Transmitted data output signal is changed at the falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Numbers of Transmit/Receive Word\nThis field specifies how many transmit/receive word numbers should be executed in one transfer.\nNote: In Slave mode with level-trigger configuration, if TX_NUM is set to 01, the slave select pin must be kept at active state during the successive data transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive word will be executed in one transfer
#01 : 1
Two successive transmit/receive words will be executed in one transfer. (burst mode)
#10 : 2
Reserved
#11 : 3
Reserved
End of enumeration elements list.
LSB : LSB First\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the TX_BIT_LEN field)
#1 : 1
LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the RX register (bit 0 of SPI_RX0/1)
End of enumeration elements list.
CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK idle low
#1 : 1
SPICLK idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\n
bits : 12 - 15 (4 bit)
access : read-write
IF : Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates the transfer dose not finish
#1 : 1
Indicates the transfer is done
End of enumeration elements list.
IE : Interrupt Enable\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI Interrupt Disabled
#1 : 1
SPI Interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Reorder Mode Select\nNote:\nByte reorder function is only available when TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, if the byte suspend function is enabled, the slave select pin must be kept at active state during the successive four bytes transfer.
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
Both byte reorder and byte suspend functions Disabled
#01 : 1
Byte reorder function Enabled, and a byte suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
#10 : 2
Byte reorder function Enabled, but byte suspend function Disabled
#11 : 3
Byte reorder function Disabled, but a suspend interval (2~17 SPICLK cycles) inserted among each byte. The setting of TX_BIT_LEN must be configured as 0x00. (32 bits/word)
End of enumeration elements list.
TWOB : Two Bits Transfer Mode Active\nNote: When TWOB is enabled, the serial transmitted 2-bit data output are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.\nNote: When TWOB is enabled, the setting of TX_NUM must be programmed as 0x00.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two-bit Transfer mode Disabled
#1 : 1
Two-bit Transfer mode Enabled
End of enumeration elements list.
VARCLK_EN : Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is enabled, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#1 : 1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER, and DIVIDER2
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThe Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and TX_NUM is set to 0x0, bit RX0[7:0] holds the received data. The values of the other bits are unknown.\nNote: The Data Receive Registers are read only.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The valid bits depend on the transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08 and the TX_NUM is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00 and TX_NUM is set to 0x1, the SPI controller will perform two 32-bit transmit/receive successive using the same setting. The transmission sequence is TX0[31:0] first and then TX1[31:0].
bits : 0 - 31 (32 bit)
access : write-only
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Variable Clock Pattern Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern\nThe value in this field is the frequency patterns of the SPI clock. If the bit pattern of VARCLK is '0', the output frequency of SPICLK is in accordance with the value of DIVIDER. If the bit patterns of VARCLK are '1', the output frequency of SPICLK is in accordance with the value of DIVIDER2. Refer to register SPI_DIVIDER.\nRefer to the Variable Serial Clock Frequency paragraph for more detailed description.
bits : 0 - 31 (32 bit)
access : read-write
SPI DMA Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DMA_GO : Transmit DMA Start\nSetting this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically.\nIf using PDMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI controller will set it automatically whenever necessary.\nHardware will clear this bit to 0 automatically after PDMA transfer done.\nNote: In DMA mode, the burst mode is not supported.
bits : 0 - 0 (1 bit)
access : read-write
RX_DMA_GO : Receive DMA Start\nSetting this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically.\nHardware will clear this bit to 0 automatically after PDMA transfer done.
bits : 1 - 1 (1 bit)
access : read-write
Clock Divider Register (Master Only)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider 1 (Master Only)\nThe value in this field is the frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIn Slave mode, the period of SPI clock driven by a master shall equal or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER2 : Clock Divider 2 (Master Only)\nThe value in this field is the 2nd frequency divider for generating the serial clock on the output SPICLK. The desired frequency is obtained according to the following equation:\n\nIf VARCLK_EN is cleared to 0, this setting is unmeaning.
bits : 16 - 31 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is also defined as slave select input in Slave mode.
bits : 0 - 1 (2 bit)
access : read-write
SS_LVL : Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select signal SPISSx0/1 is active at low-level/falling-edge
#1 : 1
Slave select signal SPISSx0/1 is active at high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select Enable Bit (Master only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing related bits in SSR[1:0]
#1 : 1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SSR[1:0], will be asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger Enable Bit (Slave only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input slave select signal is edge-trigger. This is the default value. It depends on SS_LVL to decide the signal is active at falling-edge or rising-edge
#1 : 1
Slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Accomplish Flag\nWhen the SS_LTRIG bit is set in Slave mode, this bit can be read to indicate the received bit number is met the requirement or not.\nNote: This bit is READ only.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transaction number or the transferred bit length of one transaction does not meet the specified requirements
#1 : 1
Transaction number and the transferred bit length met the specified requirements which defined in TX_NUM and TX_BIT_LEN
End of enumeration elements list.
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