\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExtEN : EBI Enable\nThis bit is the functional enable bit for EBI.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
ExtBW16 : EBI Data Width 16-bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
MCLKDIV : External Output Clock Divider\n
bits : 8 - 10 (3 bit)
access : read-write
ExttALE : Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n
bits : 16 - 18 (3 bit)
access : read-write
External Bus Interface Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExttACC : EBI Data Access Time\nExttACC defines data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write
ExttAHD : EBI Data Access Hold Time\nExttAHD defines data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
ExtIW2X : Idle State Cycle After Write\nWhen write action is finished, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write
ExtIR2R : Idle State Cycle Between Read-Read\nWhen read action is finished and the next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n
bits : 24 - 27 (4 bit)
access : read-write
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