ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPDAT

ISPCMD

ISPEN : ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Selection (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config-bits Update by ISP (Write-protection Bit)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable (Write-protection Bit)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP start trigger (Write-protection Bit) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is read only.\nFor 128KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip power on but for 64/32KB device, it is fixed at 0x0001_F000.
bits : 0 - 31 (32 bit)
access : read-only

FPSEN : Flash Power Save Enable (Write-protection Bit)\nIf CPU clock is slower than 24 MHz, software can enable flash power saving function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FATS : Flash Access Time Window Selection (Write-protection Bits)\n
bits : 1 - 3 (3 bit)
access : read-write

LFOM : Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n(This bit is only for NuMicro( NUC100/NUC120 Low Density.)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADR : ISP Address The NuMicro( NUC100 Series has a maximum of 32Kx32 embedded flash it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command\n
bits : 5 - 5 (1 bit)
access : read-write