\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x114 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Peripheral Reset Control Register 2
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USCI0RST : USCI0 Controller Reset \n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USCI0 controller normal operation
#1 : 1
USCI0 controller reset
End of enumeration elements list.
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Lock Control Code (Write)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Lock Control Disable Index (Read)
The Protected registers are:
SYS_IPRST0: address 0x5000_0008
SYS_BODCTL: address 0x5000_0018
SYS_PORCTL: address 0x5000_0024
SYS_TSOFFSET: address 0x5000_0114
CLK_PWRCTL: address 0x5000_0200 (bit[6] is not protected for power-down wake-up interrupt clear)
CLK_APBCLK0 [0]: address 0x5000_0208 (bit[0] is watchdog clock enable)
CLK_CLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)
CLK_CLKSEL1 [1:0]: address 0x5000_0214 (for watchdog clock source select)
CLK_CLKSEL3 [8]: address 0x5000_0234 (for USBD clock source select)
CLK_CLKDSTS: address 0x5000_0274
FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
FMC_ISPSTS: address 0x4000_C040
WDT_CTL: address 0x4000_4000
WDT_ALTCTL: address 0x4000_4004
FMC_FTCTL: address 0x4000_5018
FMC_ICPCMD: address 0x4000_501C
EADC_TEST: address 0x4004_3200
AHBMCTL: address 0x40000400
CLK_PLLCTL: address 0x40000240
PWM_CTL0: address 0x4005_8000
PWM_CTL0: address 0x4005_9000
PWM_DTCTL0_1: address 0x4005_8070
PWM_DTCTL0_1: address 0x4005_9070
PWM_DTCTL2_3: address 0x4005_8074
PWM_DTCTL2_3: address 0x4005_9074
PWM_DTCTL4_5: address 0x4005_8078
PWM_DTCTL4_5: address 0x4005_9078
PWM_BRKCTL0_1: address 0x4005_80C8
PWM_BRKCTL0_1: address 0x4005_90C8
PWM_BRKCTL2_3: address 0x4005_80CC
PWM_BRKCTL2_3: address 0x4005_90CC
PWM_BRKCTL4_5: address 0x4005_80D0
PWM_BRKCTL4_5: address 0x4005_90D0
PWM_INTEN1: address 0x4005_80E4
PWM_INTEN1: address 0x4005_90E4
PWM_INTSTS1: address 0x4005_80EC
PWM_INTSTS1: address 0x4005_90EC
PWM_SELFTEST: address 0x4005_8300
PWM_SELFTEST: address 0x4005_9300
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
Temperature Sensor Offset Register
address_offset : 0x114 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VTEMP : Temperature Sensor Offset Value \nThis field reflects temperature sensor output voltage offset at 25oC.\nBased on this value, with the value of temperature sensor output obtained from ADC conversion result and temperature sensor characteristics, it's easily to get temperature result by roughly calculation.
bits : 0 - 11 (12 bit)
access : read-only
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Brown-Out Detector threshold voltage is 2.2V
#01 : 1
Brown-Out Detector threshold voltage is 2.7V
#10 : 2
Brown-Out Detector threshold voltage is 3.7V
#11 : 3
Brown-Out Detector threshold voltage is 4.5V
End of enumeration elements list.
BODRSTEN : Brown-out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit.
Note1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out INTERRUPT function Enabled
#1 : 1
Brown-out RESET function Enabled
End of enumeration elements list.
BODIF : Brown-out Detector Interrupt Flag\nNote: This bit can be cleared by software writing '1'.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODLPM : Brown-out Detector Low Power Mode (Write Protect)\nNote1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BODOUT : Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled, this bit always responds 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0
#1 : 1
Brown-out Detector output status is 1
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled
End of enumeration elements list.
BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
BOD output is sampled by LIRC clock
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Without de-glitch function
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
Internal Voltage Source Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
Power-On-reset Controller Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function.\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
System Reset Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: This bit can be cleared by software writing '1'.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : NRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: This bit can be cleared by software writing '1'.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note1: This bit can be cleared by software writing '1'.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: This bit can be cleared by software writing '1'.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: This bit can be cleared by software writing '1'.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
MCURF : MCU Reset Flag
The MCU reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source.
Note: This bit can be cleared by software writing '1'.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M0
#1 : 1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: This bit can be cleared by software writing '1'.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
CPULKRF : the CPULK Reset Flag Is Set by Hardware If Cortex-M0 Lockup Happened\nNote: This bit can be cleared by software writing '1'.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU lockup happened
#1 : 1
The Cortex-M0 lockup happened and chip is reset
End of enumeration elements list.
GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC1MFP : PC.1 Multi-function Pin Selection.
bits : 4 - 7 (4 bit)
access : read-write
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Peripheral Reset Control Register 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA controller normal operation
#1 : 1
PDMA controller reset
End of enumeration elements list.
HIRC Trim Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN(SYS_IRCTCTL1[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Reserved
#10 : 2
Enable HIRC auto trim function and trim HIRC to 48 MHz
#11 : 3
Reserved
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many clocks of reference clock .\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 clocks of reference clock
#01 : 1
Trim value calculation is based on average difference in 8 clocks of reference clock
#10 : 2
Trim value calculation is based on average difference in 16 clocks of reference clock
#11 : 3
Trim value calculation is based on average difference in 32 clocks of reference clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL(SYS_IRCTCTL1[1:0]) will be cleared to 00.\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit\nNote1: CESTOPEN is set to 0 and FREQLOCK is set to 1, CLKERRIF will be set to 1 once and auto-trim function will stop trimming HIRC until LXT or SOF works normally.\nNote2: After FREQLOCK is set to 1, CLKERRIF will be set to 1 only once and RC_TRIM will hang on and stop trimming RC until a reference clock is recovered when CESTOPEN is 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
REFCKSEL : Reference Clock Selection\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim reference clock is from LXT (32.768 kHz)
#1 : 1
HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet
End of enumeration elements list.
HIRC Trim Interrupt Enable Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : HIRC Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL1[1:0]).\nIf this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : HIRC Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC Trim Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.\nWrite 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed RC oscillator 1 frequency doesn't lock at 48 MHz yet
#1 : 1
The internal high-speed RC oscillator 1 frequency locked at 48 MHz
End of enumeration elements list.
TFAILIF : HIRC Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRCTIEN1[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC trim value update limitation count does not reach
#1 : 1
HIRC trim value update limitation count reached and frequency still not locked
End of enumeration elements list.
CLKERRIF : HIRC Clock Error Interrupt Status\nWhen the frequency of SOF or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRCTIEN1[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC Clock frequency is accuracy
#1 : 1
HIRC Clock frequency is inaccuracy
End of enumeration elements list.
Peripheral Reset Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
BPWM0RST : BPWM0 Controller Reset \n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0 controller normal operation
#1 : 1
BPWM0 controller reset
End of enumeration elements list.
BPWM1RST : BPWM1 Controller Reset \n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM1 controller normal operation
#1 : 1
BPWM1 controller reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset \n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 controller normal operation
#1 : 1
PWM0 controller reset
End of enumeration elements list.
PWM1RST : PWM1 Controller Reset \n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 controller normal operation
#1 : 1
PWM1 controller reset
End of enumeration elements list.
USBDRST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB device controller normal operation
#1 : 1
USB device controller reset
End of enumeration elements list.
ADCRST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC controller normal operation
#1 : 1
ADC controller reset
End of enumeration elements list.
Modulation Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEN : Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with BPWM2 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Modulation Function Disabled
#1 : 1
Modulation Function Enabled
End of enumeration elements list.
MODH : Modulation at Data High\nSelect modulation pulse(BPWM2) at UART0_TXD high or low\n0: Modulation pulse at UART0_TXD or USCI0_DAT0 low.\n1: Modulation pulse at UART0_TXD or USCI0_DAT0 high.
bits : 1 - 1 (1 bit)
access : read-write
MODPWMSEL : BPWM2 Channel Select for Modulation\nSelect the BPWM2 channel to modulate with the UART0_TXD or USCI0_DAT0.\n0000: BPWM2 Channel 0 modulate with UART0_TXD.\n0001: BPWM2 Channel 1 modulate with UART0_TXD.\n0010: BPWM2 Channel 2 modulate with UART0_TXD.\n0011: BPWM2 Channel 3 modulete with UART0_TXD.\n0100: BPWM2 Channel 4 modulete with UART0_TXD.\n0101: BPWM2 Channel 5 modulete with UART0_TXD.\n0110: Reserved.\n0111: Reserved.\n1000: BPWM2 Channel 0 modulate with USCI0_DAT0.\n1001: BPWM2 Channel 1 modulate with USCI0_DAT0.\n1010: BPWM2 Channel 2 modulate with USCI0_DAT0.\n1011: BPWM2 Channel 3 modulete with USCI0_DAT0.\n1100: BPWM2 Channel 4 modulete with USCI0_DAT0.\n1101: BPWM2 Channel 5 modulete with USCI0_DAT0.\n1110: Reserved.\n1111: Reserved.\nNote: This bis is valid while MODEN (SYS_MODCTL[0]) is set to 1.
bits : 4 - 7 (4 bit)
access : read-write
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