Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
USB Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_IE : Bus Event Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable BUS event interrupt
#1 : 1
Enable BUS event interrupt
End of enumeration elements list.
USB_IE : USB Event Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable USB event interrupt
#1 : 1
Enable USB event interrupt
End of enumeration elements list.
FLDET_IE : Floating Detected Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Floating detect Interrupt
#1 : 1
Enable Floating detect Interrupt
End of enumeration elements list.
WAKEUP_IE : USB Wake-Up Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable USB wake-up Interrupt
#1 : 1
Enable USB wake-up Interrupt
End of enumeration elements list.
WAKEUP_EN : Wake-Up Function Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable USB wake-up function
#1 : 1
Enable USB wake-up function
End of enumeration elements list.
INNAK_EN : Active NAK Function and its Status in IN Token
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The NAK status doesn't be updated into the endpoint status register when it was set to 0. It also disable the interrupt event when device responds NAK after receiving IN token
#1 : 1
The NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enable the interrupt event when the device responds NAK after receiving IN token
End of enumeration elements list.
USB Bus Status and Attribution Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBRST : USB Reset Status\nIt is a read only bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus no reset
#1 : 1
Bus reset when SE0 (single-ended 0) more than 2.5us
End of enumeration elements list.
SUSPEND : Suspend Status\nIt is a read only bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus no suspend
#1 : 1
Bus idle more than 3 ms, either cable is plugged off or host is sleeping
End of enumeration elements list.
RESUME : Resume Status\nIt is a read only bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus resume
#1 : 1
Resume from suspend
End of enumeration elements list.
TIMEOUT : Time-Out Status\nIt is a read only bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No time-out
#1 : 1
Bus no any response more than 18 bits time
End of enumeration elements list.
PHY_EN : PHY Transceiver Function Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PHY transceiver function
#1 : 1
Enable PHY transceiver function
End of enumeration elements list.
RWAKEUP : Remote Wake-Up
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Release the USB bus from K state
#1 : 1
Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up
End of enumeration elements list.
USB_EN : USB Controller Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable USB Controller
#1 : 1
Enable USB Controller
End of enumeration elements list.
DPPU_EN : Pull-up Resistor on USB_DP Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the pull-up resistor in USB_DP bus
#1 : 1
The pull-up resistor in USB_DP bus active
End of enumeration elements list.
PWRDN : Power Down PHY Transceiver (low active)
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
power down related circuit of PHY transceiver
#1 : 1
Turn-on related circuit of PHY transceiver
End of enumeration elements list.
BYTEM : CPU access USB SRAM Size Mode Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word Mode: The size of the transfer from CPU to USB SRAM can be Word only
#1 : 1
Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only
End of enumeration elements list.
USB Floating Detected Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLDET : Device Floating Detected
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The controller didn't attached into the USB host
#1 : 1
When the controller is attached into the BUS, this bit will be set as 1
End of enumeration elements list.
Setup Token Buffer Segmentation Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEG : It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only.
bits : 3 - 8 (6 bit)
access : read-write
Endpoint 0 Buffer Segmentation Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEGx : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is\nUSB_SRAM address + {BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write
Endpoint 0 Maximal Payload Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPLD : Maximal Payload
It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1). When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2). When the register is read by CPU,
For IN token, the value of MXPLD is indicated the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note that once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write
Endpoint 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_NUM : Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
bits : 0 - 3 (4 bit)
access : read-write
ISOCH : Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Isochronous endpoint
#1 : 1
Isochronous endpoint
End of enumeration elements list.
STATE : Endpoint STATE
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 0
Endpoint is disabled
#01 : 1
Out endpoint
#10 : 2
IN endpoint
#11 : 3
Undefined
End of enumeration elements list.
DSQ_SYNC : Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DATA0 PID
#1 : 1
DATA1 PID
End of enumeration elements list.
CSTALL : Clear STALL Response
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the device to clear the STALL handshake in setup stage
#1 : 1
Clear the device to response STALL handshake in setup stage
End of enumeration elements list.
Endpoint 0 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRRDY : Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it is auto clear to 0.\nFor IN token, write '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, write '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is write 1 only and it is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : read-write
SSTALL : Set STALL
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the device to response STALL
#1 : 1
Set the device to respond STALL automatically
End of enumeration elements list.
Endpoint 1 Buffer Segmentation Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Maximal Payload Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Configuration Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Interrupt Event Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_STS : BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No any BUS event is occurred
#1 : 1
Bus event occurred check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0]
End of enumeration elements list.
USB_STS : USB Event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No any USB event is occurred
#1 : 1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31])
End of enumeration elements list.
FLDET_STS : Floating Detected Interrupt Status
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is not attached/detached event in the USB
#1 : 1
There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2]
End of enumeration elements list.
WAKEUP_STS : Wake-Up Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wake-up event is occurred
#1 : 1
Wake-up event occurred, cleared by write 1 to USB_INTSTS[3]
End of enumeration elements list.
EPEVT0 : Endpoint 0's USB Event Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 0
#1 : 1
USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT1 : Endpoint 1's USB Event Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 1
#1 : 1
USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT2 : Endpoint 2's USB Event Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 2
#1 : 1
USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT3 : Endpoint 3's USB Event Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 3
#1 : 1
USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT4 : Endpoint 4's USB Event Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 4
#1 : 1
USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT5 : Endpoint 5's USB Event Status
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 5
#1 : 1
USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1]
End of enumeration elements list.
SETUP : Setup Event Status
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Setup event
#1 : 1
Setup event occurred, cleared by write 1 to USB_INTSTS[31]
End of enumeration elements list.
Endpoint 2 Buffer Segmentation Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Maximal Payload Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Configuration Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Buffer Segmentation Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Maximal Payload Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Configuration Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Buffer Segmentation Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Maximal Payload Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Configuration Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Buffer Segmentation Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Maximal Payload Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Configuration Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Device Function Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADDR : USB device's Function Address
bits : 0 - 6 (7 bit)
access : read-write
USB Drive SE0 Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRVSE0 : Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
None
#1 : 1
Force USB PHY transceiver to drive SE0
End of enumeration elements list.
USB Endpoint Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVERRUN : Overrun\nIt indicates that the received data is over the maximum payload number or not.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun
#1 : 1
It indicates that the Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes
End of enumeration elements list.
EPSTS0 : Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS1 : Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 11 - 13 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS2 : Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 14 - 16 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS3 : Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS4 : Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 20 - 22 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS5 : Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint
bits : 23 - 25 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.