GPIO

PIN0 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B/C/D] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low
bits : 15 - 15 (1 bit)
access : read-only

GPIOA_DBEN

GPIO Port A De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN0 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN4 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN5 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN6 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN7 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN8 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN9 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN10 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN11 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN12 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN13 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN14 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN15 : Port [A/B/C/D] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

GPIOA_IMD

GPIO Port A Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMD0 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD6 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD7 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD8 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD9 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD10 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD11 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD12 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD13 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD14 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD15 : Port [A/B/C/D] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

DBNCECON

De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the internal 10 KHz low speed clock

End of enumeration elements list.

ICLK_ON : Interrupt Clock On Mode\nSet this bit to 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the clock if the GPIOA/B/C/D[n] interrupt is disabled

#1 : 1

Interrupt generated circuit clock always enable

End of enumeration elements list.

GPIOA_IEN

GPIO Port A Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IF_EN0 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN4 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN5 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN6 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN7 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN8 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN9 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN10 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN11 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN12 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN13 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN14 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IF_EN15 : Port [A/B/C/D] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] state low-level or high-to-low change interrupt

#1 : 1

Enable the PIN[n] state low-level or high-to-low change interrupt

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN4 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN5 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN6 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN7 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN8 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN9 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN11 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN12 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN13 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN14 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

IR_EN15 : Port [A/B/C/D] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IR_EN[n] bit to 1: If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the PIN[n] level-high or low-to-high interrupt

#1 : 1

Enable the PIN[n] level-high or low-to-high interrupt

End of enumeration elements list.

GPIOA_ISRC

GPIO Port A Interrupt Trigger Source Indicator
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISRC0 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC4 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC5 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC6 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC7 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC8 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC9 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC10 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC11 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC12 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC13 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC14 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

ISRC15 : Port [A/B/C/D] Interrupt Trigger Source Indicator\nRead :
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n]\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt\nClear the correspond pending interrupt

End of enumeration elements list.

GPIOA0_DOUT

GPIO PA.0 Bit Output/Input Value
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOxx_DOUT : GPIOxx I/O Pin Bit Output/Input Control\nWrite this bit can control one GPIO pin output value\nRead this register to get IO pin status.\nFor example: write GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0].
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set corresponding GPIO pin to low

#1 : 1

Set corresponding GPIO pin to high

End of enumeration elements list.

GPIOA1_DOUT

GPIO PA.1 Bit Output/Input Value
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA2_DOUT

GPIO PA.2 Bit Output/Input Value
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA3_DOUT

GPIO PA.3 Bit Output/Input Value
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA4_DOUT

GPIO PA.4 Bit Output/Input Value
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA5_DOUT

GPIO PA.5 Bit Output/Input Value
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA6_DOUT

GPIO PA.6 Bit Output/Input Value
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA7_DOUT

GPIO PA.7 Bit Output/Input Value
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA8_DOUT

GPIO PA.8 Bit Output/Input Value
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA9_DOUT

GPIO PA.9 Bit Output/Input Value
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA10_DOUT

GPIO PA.10 Bit Output/Input Value
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA11_DOUT

GPIO PA.11 Bit Output/Input Value
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA12_DOUT

GPIO PA.12 Bit Output/Input Value
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA13_DOUT

GPIO PA.13 Bit Output/Input Value
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA14_DOUT

GPIO PA.14 Bit Output/Input Value
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA15_DOUT

GPIO PA.15 Bit Output/Input Value
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB0_DOUT

GPIO PB.0 Bit Output/Input Value
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB1_DOUT

GPIO PB.1 Bit Output/Input Value
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB2_DOUT

GPIO PB.2 Bit Output/Input Value
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB3_DOUT

GPIO PB.3 Bit Output/Input Value
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB4_DOUT

GPIO PB.4 Bit Output/Input Value
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB5_DOUT

GPIO PB.5 Bit Output/Input Value
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB6_DOUT

GPIO PB.6 Bit Output/Input Value
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB7_DOUT

GPIO PB.7 Bit Output/Input Value
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB8_DOUT

GPIO PB.8 Bit Output/Input Value
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB9_DOUT

GPIO PB.9 Bit Output/Input Value
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB10_DOUT

GPIO PB.10 Bit Output/Input Value
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB11_DOUT

GPIO PB.11 Bit Output/Input Value
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB12_DOUT

GPIO PB.12 Bit Output/Input Value
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB13_DOUT

GPIO PB.13 Bit Output/Input Value
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB14_DOUT

GPIO PB.14 Bit Output/Input Value
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB15_DOUT

GPIO PB.15 Bit Output/Input Value
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC0_DOUT

GPIO PC.0 Bit Output/Input Value
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC1_DOUT

GPIO PC.1 Bit Output/Input Value
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC2_DOUT

GPIO PC.2 Bit Output/Input Value
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC3_DOUT

GPIO PC.3 Bit Output/Input Value
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC4_DOUT

GPIO PC.4 Bit Output/Input Value
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC5_DOUT

GPIO PC.5 Bit Output/Input Value
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC6_DOUT

GPIO PC.6 Bit Output/Input Value
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC7_DOUT

GPIO PC.7 Bit Output/Input Value
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC8_DOUT

GPIO PC.8 Bit Output/Input Value
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC9_DOUT

GPIO PC.9 Bit Output/Input Value
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC10_DOUT

GPIO PC.10 Bit Output/Input Value
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC11_DOUT

GPIO PC.11 Bit Output/Input Value
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC12_DOUT

GPIO PC.12 Bit Output/Input Value
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC13_DOUT

GPIO PC.13 Bit Output/Input Value
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC14_DOUT

GPIO PC.14 Bit Output/Input Value
address_offset : 0x2B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC15_DOUT

GPIO PC.15 Bit Output/Input Value
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD0_DOUT

GPIO PD.0 Bit Output/Input Value
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD1_DOUT

GPIO PD.1 Bit Output/Input Value
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD2_DOUT

GPIO PD.2 Bit Output/Input Value
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD3_DOUT

GPIO PD.3 Bit Output/Input Value
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD4_DOUT

GPIO PD.4 Bit Output/Input Value
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD5_DOUT

GPIO PD.5 Bit Output/Input Value
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD6_DOUT

GPIO PD.6 Bit Output/Input Value
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD7_DOUT

GPIO PD.7 Bit Output/Input Value
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD8_DOUT

GPIO PD.8 Bit Output/Input Value
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD9_DOUT

GPIO PD.9 Bit Output/Input Value
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD10_DOUT

GPIO PD.10 Bit Output/Input Value
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD11_DOUT

GPIO PD.11 Bit Output/Input Value
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD12_DOUT

GPIO PD.12 Bit Output/Input Value
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD13_DOUT

GPIO PD.13 Bit Output/Input Value
address_offset : 0x2F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD14_DOUT

GPIO PD.14 Bit Output/Input Value
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD15_DOUT

GPIO PD.15 Bit Output/Input Value
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_OFFD

GPIO Port A Pin OFF Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFD : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, users can OFF digital input path to avoid creepage,
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

Enable IO digital input path

1 : 1

Disable IO digital input path (digital input tied to low)

End of enumeration elements list.

GPIOB_PMD

GPIO Port B Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_OFFD

GPIO Port B Pin OFF Digital Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DOUT

GPIO Port B Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DMASK

GPIO Port B Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_PIN

GPIO Port B Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DBEN

GPIO Port B De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IMD

GPIO Port B Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IEN

GPIO Port B Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_ISRC

GPIO Port B Interrupt Trigger Source Indicator
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DOUT

GPIO Port A Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT4 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT5 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT6 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT7 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT8 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT9 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT11 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT12 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT13 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT14 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

DOUT15 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-bidirectional mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

#1 : 1

GPIO port [A/B/C/D] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-bidirectional mode

End of enumeration elements list.

GPIOC_PMD

GPIO Port C Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_OFFD

GPIO Port C Pin OFF Digital Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DOUT

GPIO Port C Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DMASK

GPIO Port C Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_PIN

GPIO Port C Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DBEN

GPIO Port C De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IMD

GPIO Port C Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IEN

GPIO Port C Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_ISRC

GPIO Port C Interrupt Trigger Source Indicator
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DMASK

GPIO Port A Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASK0 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK4 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK5 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK6 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK7 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK8 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK9 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK10 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK11 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK12 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK13 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK14 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK15 : Port [A/B/C/D] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n] . When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT).
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

GPIOD_PMD

GPIO Port D Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_OFFD

GPIO Port D Pin OFF Digital Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DOUT

GPIO Port D Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DMASK

GPIO Port D Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_PIN

GPIO Port D Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DBEN

GPIO Port D De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IMD

GPIO Port D Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IEN

GPIO Port D Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_ISRC

GPIO Port D Interrupt Trigger Source Indicator
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

GPIO

Peripheral Memory Blocks

Registers

GPIOA_PMD

GPIOA_PIN

GPIOA_DBEN

GPIOA_IMD

DBNCECON

GPIOA_IEN

GPIOA_ISRC

GPIOA0_DOUT

GPIOA1_DOUT

GPIOA2_DOUT

GPIOA3_DOUT

GPIOA4_DOUT

GPIOA5_DOUT

GPIOA6_DOUT

GPIOA7_DOUT

GPIOA8_DOUT

GPIOA9_DOUT

GPIOA10_DOUT

GPIOA11_DOUT

GPIOA12_DOUT

GPIOA13_DOUT

GPIOA14_DOUT

GPIOA15_DOUT

GPIOB0_DOUT

GPIOB1_DOUT

GPIOB2_DOUT

GPIOB3_DOUT

GPIOB4_DOUT

GPIOB5_DOUT

GPIOB6_DOUT

GPIOB7_DOUT

GPIOB8_DOUT

GPIOB9_DOUT

GPIOB10_DOUT

GPIOB11_DOUT

GPIOB12_DOUT

GPIOB13_DOUT

GPIOB14_DOUT

GPIOB15_DOUT

GPIOC0_DOUT

GPIOC1_DOUT

GPIOC2_DOUT

GPIOC3_DOUT

GPIOC4_DOUT

GPIOC5_DOUT

GPIOC6_DOUT

GPIOC7_DOUT

GPIOC8_DOUT

GPIOC9_DOUT

GPIOC10_DOUT

GPIOC11_DOUT

GPIOC12_DOUT

GPIOC13_DOUT

GPIOC14_DOUT

GPIOC15_DOUT

GPIOD0_DOUT

GPIOD1_DOUT

GPIOD2_DOUT

GPIOD3_DOUT

GPIOD4_DOUT

GPIOD5_DOUT

GPIOD6_DOUT

GPIOD7_DOUT

GPIOD8_DOUT

GPIOD9_DOUT

GPIOD10_DOUT

GPIOD11_DOUT

GPIOD12_DOUT

GPIOD13_DOUT

GPIOD14_DOUT

GPIOD15_DOUT

GPIOA_OFFD

GPIOB_PMD

GPIOB_OFFD

GPIOB_DOUT

GPIOB_DMASK