TCSR2

TCSR3

TCMPR3

TISR3

TDR3

TCMPR2

TISR2

TDR2

PRESCALE : Pre-scale Counter
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTB : Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 5.10.4.5 for detail description.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACT : Timer Active Status Bit (Read only)\nThis bit indicates the 24-bit up counter status.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRST : Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Timer Operating Mode
bits : 27 - 28 (2 bit)
access : read-write

IE : Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal (TIF) when the associated up-timer value is equal to TCMPR.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CEN : Timer Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_TMR : ICE Debug Mode Acknowledge Disable (write-protection bit)\nTIMER counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software.
bits : 0 - 0 (1 bit)
access : read-write

TDR : Timer Data Register\nWhen TCSR.TDR_EN is set to 1, the internal 24-bit up-timer value will be loaded into TDR. User can read this register for the up-timer value.
bits : 0 - 23 (24 bit)
access : read-only