ISPCON

ISPTRG

FATCON

ISPADR

ISPDAT

ISPCMD

ISPEN : ISP Enable (write-protection bit)\nISP function enable bit. Set this bit to enable ISP function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (write-protection bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config-bits Update by ISP (write-protection bit)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable (write-protection bit)\nLDROM update enable bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (write-protection bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself \n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

PT : Flash Program Time (write-protection bits)
bits : 8 - 10 (3 bit)
access : read-write

ET : Flash Erase Time (write-protection bits)
bits : 12 - 14 (3 bit)
access : read-write

ISPGO : ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LFOM : Low Frequency Optimization Mode (write-protection bit) If chip operation frequency lower than 20 MHz, chip can work more efficiently when this bit is set to 1. If chip operation frequency is 40 MHz, both of LFOM and MFOM have to set to zero.
bits : 4 - 4 (1 bit)
access : read-write

MFOM : Middle Frequency Optimization Mode (write-protection bit) If chip operation frequency is between 20 MHz ~ 40 MHz, chip can work more efficiently when this bit is set to 1. If chip operation frequency is 40 MHz, both of LFOM and MFOM have to set to zero.
bits : 6 - 6 (1 bit)
access : read-write

ISPADR : ISP Address\nNuMicro( NUC122 Series equips with a maximum 16Kx32 embedded flash, it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

FCTRL : ISP Command
bits : 0 - 3 (4 bit)
access : read-write

FCEN : ISP Command
bits : 4 - 4 (1 bit)
access : read-write

FOEN : ISP Command
bits : 5 - 5 (1 bit)
access : read-write