\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : SPI Transfer Control Bit and Busy Status\nIf the FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In slave mode, this bit always returns 1 when software reads this register. In master mode, this bit reflects the busy or idle status of SPI.\nNotes:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.\nWhen FIFO mode is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA block finishes the data transfer.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transfer stopped if SPI is transferring
#1 : 1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive on Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising edge of SPICLK
#1 : 1
Received data input signal is latched on the falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit on Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising edge of SPICLK
#1 : 1
Transmitted data output signal is changed on the falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.
bits : 3 - 7 (5 bit)
access : read-write
LSB : LSB First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register depending on the TX_BIT_LEN field)
#1 : 1
The LSB, bit 0 of the SPI TX0/1 register is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX0/1)
End of enumeration elements list.
CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPICLK idle low
#1 : 1
SPICLK idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\nThese four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation:\n (SP_CYCLE[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\nIf the variable clock function is enabled and the transmit FIFO buffer is not empty, the minimum period of suspend interval between the successive transactions is (6.5 + SP_CYCLE) * SPICLK clock cycle.
bits : 12 - 15 (4 bit)
access : read-write
IF : Transfer Done Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
It indicates that the transfer does not finish yet
#1 : 1
It indicates that the SPI controller has finished one unit transfer
End of enumeration elements list.
IE : Transfer Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI transfer done Interrupt Disabled
#1 : 1
SPI transfer done Interrupt Enabled
End of enumeration elements list.
SLAVE : Slave mode
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Mode Function\nNotes:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.\nThe byte reorder function is not supported when the variable serial clock function or the dual I/O mode is enabled.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte reorder functions Disabled
#1 : 1
Byte reorder function Enabled and a byte suspend interval inserted among each byte depending on the setting of SP_CYCLE. The period of the byte suspend interval depends on the setting of SP_CYCLE
End of enumeration elements list.
FIFO : FIFO Mode
Notes:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set 1 automatically after the data was written into the 8-depth FIFO. It means all data stored at transmit FIFO buffer are transferred when the transmit FIFO buffer is empty and the GO_BUSY bit back to 0..
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO mode Disabled
#1 : 1
FIFO mode Enabled
End of enumeration elements list.
TWOB : Two-Bit Transfer Mode Enable\nNote: When TWOB is enabled, the serial transmitted 2-bit data are from SPI_TX1/0, and the received 2-bit data input are put in SPI_RX1/0.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Two-bit transfer mode Disabled
#1 : 1
Two-bit transfer mode Enabled
End of enumeration elements list.
VARCLK_EN : Variable Clock Enable (Master Only)\nNote: When this VARCLK_EN bit is set to 1, the setting of TX_BIT_LEN must be programmed as 0x10 (16-bit mode)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Serial clock output frequency is fixed and decided only by the value of DIVIDER
#1 : 1
Serial clock output frequency is variable. The output frequency is decided by the value of VARCLK, DIVIDER1, and DIVIDER2
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIFO buffer is not empty
#1 : 1
Indicates that the receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (read only)\nIt's a mutual mirror bit of SPI_STATUS[25].
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIOF buffer is not full
#1 : 1
Indicates that the receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (read only)\nIt's a mutual mirror bit of SPI_STAUTS[26].
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not empty
#1 : 1
Indicates that the transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_STATUS[27].
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not full
#1 : 1
Indicates that the transmit FIFO buffer is full
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, the software can access the receive FIFO buffer by reading this register. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depend on the setting of transmit bit length field in the CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit TX0[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: when the SPI controller is configured as a slave device and the FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the software must update the transmit data register before setting the GO_BUSY bit to 1.
bits : 0 - 31 (32 bit)
access : write-only
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Variable Clock Pattern Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern
This register defines the clock pattern of the SPI transfer. If the variable clock function is disabled, this setting is unmeaning. Refer to the Variable Clock Function paragraph for more detail description.
bits : 0 - 31 (32 bit)
access : read-write
SPI DMA Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DMA_GO : Transmit DMA Start\nSet this bit to 1 will start the transmit PDMA process. SPI controller will issue request to PDMA controller automatically. Hardware will clear this bit to 0 automatically after PDMA transfer done.\nIf uses SPI transmit PDMA function to transfer data, the software should not set the GO_BUSY bit to 1. The PDMA control logic of SPI controller will set it automatically whenever necessary.\nIn slave mode and the FIFO mode is disabled, the minimal suspend interval between two successive transactions must be larger than (8 SPI serial clock periods + 14 APB clock periods) for edge-trigger mode or (9.5 serial clock periods + 14 APB clock periods) for level-trigger mode. If the 2-bit transfer mode is enabled, additional 18 APB clock periods for the above conditions is required.
bits : 0 - 0 (1 bit)
access : read-write
RX_DMA_GO : Receive DMA Start\nSet this bit to 1 will start the receive PDMA process. SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty. Hardware will clear this bit to 0 automatically after PDMA transfer is done.\nIf the software uses the receive PDMA function to access the received data of SPI and does not use the transmit PDMA function, the GO_BUSY bit shall be set by software.\nEnable the FIFO mode is recommended if the software uses more than one PDMA channel to transfer data.\nIn slave mode and the FIFO mode is disabled, if the software only uses one PDMA channel for SPI receive PDMA function and the other PDMA channels are not in use, the minimal suspend interval between two successive transactions must be larger than (9 SPI slave engine clock periods + 4 APB clock periods) for edge-trigger mode or (9.5 SPI slave engine clock periods + 4 APB clock periods) for level-trigger mode.
bits : 1 - 1 (1 bit)
access : read-write
PDMA_RST : PDMA Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Reset PDMA. Reset Disabled
#1 : 1
Reset the PDMA control logic in this SPI controller. This bit will be cleared to 0 automatically
End of enumeration elements list.
Control and Status Register 2
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOSLVSEL : No Slave Selected (3-Wire) in Slave mode\nThis is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.\nNote: In No Slave Select Signal mode, the SS_LTRIG, SPI_SSR[4], will be set as 1 automatically.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-direction interface
#1 : 1
3-wire bi-direction interface
End of enumeration elements list.
SLV_ABORT : Slave 3-Wire Mode Abort Control Bit\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more serial clock input over the one transfer time in slave 3-wire mode, the user can set this bit to force the current transfer done and then the user can get a transfer done interrupt event. \nNote: It will be cleared to 0 automatically by hardware after the software sets this bit to 1
bits : 9 - 9 (1 bit)
access : read-write
SSTA_INTEN : Slave 3-Wire Mode Start Interrupt Enable\nIt is used to enable interrupt when the transfer has started in slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the transfer start interrupt
#1 : 1
Enable the transaction start interrupt. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
End of enumeration elements list.
SLV_START_INTSTS : Slave 3-Wire Mode Start Interrupt Status\nIt indicates that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_STATUS[11].
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
It indicates that the SPI transfer is not active
#1 : 1
It indicates that the transfer start in slave mode with no slave select. It will be cleared automatically when the transfer is done or writing one to this bit
End of enumeration elements list.
DUAL_IO_DIR : Dual IO Mode Direction
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dual input mode
#1 : 1
Dual output mode
End of enumeration elements list.
DUAL_IO_EN : Dual IO Mode
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dual IO Mode function Disabled
#1 : 1
Dual IO Mode function Enabled
End of enumeration elements list.
SS_INT_OPT : Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#1 : 1
As the slave select signal goes to inactive level, the IF bit will be set to 1
End of enumeration elements list.
BCn : SPI Engine Clock Backward Compatible Option\nRefer to the description of SPI_DIVIDER register for details.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Backward compatible clock configuration
#1 : 1
The clock configuration is not backward compatible
End of enumeration elements list.
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI engine clock, fspi_eclk, and the SPI serial clock of SPI master. The frequency is obtained according to the following equation:\nIf the bit of BCn, SPI_CNTR2[31], is set to'0'.\n\nelse if BCn is set to '1',\n_\nwhere \n is the SPI engine clock source. It is defined in the CLK_SEL1 register.
bits : 0 - 7 (8 bit)
access : read-write
DIVIDER2 : Clock Divider 2 Register (Master Only)\nThe value in this field is the 2nd frequency divider for generating the second clock of the variable clock function. The frequency is obtained according to the following equation:\n\nIf the VARCLK_EN bit is cleared to 0, this setting is unmeaning.
bits : 16 - 23 (8 bit)
access : read-write
FIFO Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CLR : Clear Receive FIFO Buffer
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
Clear Receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect
End of enumeration elements list.
TX_CLR : Clear Transmit FIFO Buffer
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#1 : 1
Clear Transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after software sets it to 1.0 = No effect
End of enumeration elements list.
RX_INTEN : RX Threshold Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#1 : 1
RX threshold interrupt Enabled.0 = RX threshold interrupt Disabled
End of enumeration elements list.
TX_INTEN : TX Threshold Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#1 : 1
TX threshold interrupt Enabled.0 = TX threshold interrupt Disabled
End of enumeration elements list.
RXOV_INTEN : Receive FIFO Over Run Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO over run interrupt Disabled
#1 : 1
Receive FIFO over run interrupt Enabled
End of enumeration elements list.
TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out function Disabled
#1 : 1
Time-out function Enabled
End of enumeration elements list.
RXTHRESHOLD : Received FIFO Threshold\n\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write
TXTHRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write
SPI Status Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
It indicates that the valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RX_THRESHOLD
#1 : 1
It indicates that the valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
End of enumeration elements list.
RX_OVER_RUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
It indicates that the valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#1 : 1
It indicates that the valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
End of enumeration elements list.
SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate that the transfer has started in slave 3-wire mode. It's a mutual mirror bit of SPI_CNTRL2[11].
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
It indicates that the transfer is not started
#1 : 1
It indicates that the transfer has started in slave 3-wire mode. It will be cleared as transfer done or by writing one to this bit
End of enumeration elements list.
RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nIndicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only
IF : SPI Unit Transfer Interrupt Flag\nIt's a mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
It indicates that the transfer does not finish yet
#1 : 1
It indicates that the SPI controller has finished one unit transfer
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
It indicates that the receive FIFO buffer is not empty and there is not be read over 64 SPI clock period in master mode and over 576 SPI engine clock period in slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIFO buffer is not empty
#1 : 1
Indicates that the receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[24].
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the receive FIFO buffer is not empty
#1 : 1
Indicates that the receive FIFO buffer is empty
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[26].
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not empty
#1 : 1
Indicates that the transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nIt's a mutual mirror bit of SPI_CNTRL[27].
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
Indicates that the transmit FIFO buffer is not full
#1 : 1
Indicates that the transmit FIFO buffer is full
End of enumeration elements list.
TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nIndicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Control Bits (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 0 to any bit location of this field will keep the corresponding SPISSx0/1 line at inactive state writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. The active state of SPISSx0/1 is specified in SS_LVL.
Note: SPISSx0 is defined as the slave select input in Slave mode.
bits : 0 - 1 (2 bit)
access : read-write
SS_LVL : Slave Select Active Level\nIt defines the active status of slave select signal (SPISSx0/1).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPISSx0/1 is active on low-level/falling-edge
#1 : 1
The slave select signal SPISSx0/1 is active on high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select (Master only)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[1:0]
#1 : 1
If this bit is set, SPISSx0/1 signals will be generated automatically. It means that device/slave select signal, which is set in SPI_SSR[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger (Slave only)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input slave select signal is edge-trigger. This is the default value. It depends on the SS_LVL bit to decide the signal is active at falling-edge or rising-edge
#1 : 1
Slave select signal will be level-trigger, which depends on the SS_LVL bit to decide the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Accomplish Flag\nIn slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is READ only. As the software sets the GO_BUSY bit to 1, the LTRIG_FLAG will be cleared to 0 after 4 SPI engine clock periods plus 1 system clock period. In FIFO mode, this bit is unmeaning.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transferred bit length of one transaction does not meet the specified requirement
#1 : 1
The transferred bit length meets the specified requirement which defined in TX_BIT_LEN
End of enumeration elements list.
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