DMA_GCRCSR

DMA_PDSSR2

DMA_PDSSR0

DMA_PDSSR1

DMA_GCRISR

CLK0_EN : PDMA Controller Channel 0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK1_EN : PDMA Controller Channel 1 Clock Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK2_EN : PDMA Controller Channel 2 Clock Enable Control
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK3_EN : PDMA Controller Channel 3 Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK4_EN : PDMA Controller Channel 4 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK5_EN : PDMA Controller Channel 5 Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_CLK_EN : CRC Controller Clock Enable Control
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_RXSEL : PDMA I2S RX Selection This filed defines which PDMA channel is connected to the on-chip peripheral I2S RX. Software can change the channel RX setting by I2S_RXSEL 4'b0000: CH0 4'b0001: CH1 4'b0010: CH2 4'b0011: CH3 4'b0100: CH4 4'b0101: CH5 Others : Reserved
bits : 0 - 3 (4 bit)
access : read-write

I2S_TXSEL : PDMA I2S TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral I2S TX. Software can configure the TX channel setting by I2S_TXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 4 - 7 (4 bit)
access : read-write

PWM0_RXSEL : PDMA PWM0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX. Software can configure the RX channel setting by PWM0_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 8 - 11 (4 bit)
access : read-write

PWM1_RXSEL : PDMA PWM1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX. Software can configure the RX channel setting by PWM1_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 12 - 15 (4 bit)
access : read-write

PWM2_RXSEL : PDMA PWM2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM2 RX. Software can configure the RX channel setting by PWM2_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 16 - 19 (4 bit)
access : read-write

PWM3_RXSEL : PDMA PWM3 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral PWM3 RX. Software can configure the RX channel setting by PWM3_RXSEL. The channel configuration is the same as I2S_RXSEL field. Please refer to the explanation of I2S_RXSEL.
bits : 20 - 23 (4 bit)
access : read-write

SPI0_RXSEL : PDMA SPI0 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 RX. Software can change the channel RX setting by SPI0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers: Reserved
bits : 0 - 3 (4 bit)
access : read-write

SPI0_TXSEL : PDMA SPI0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI0 TX. Software can configure the TX channel setting by SPI0_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 4 - 7 (4 bit)
access : read-write

SPI1_RXSEL : PDMA SPI1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 RX. Software can configure the RX channel setting by SPI1_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 8 - 11 (4 bit)
access : read-write

SPI1_TXSEL : PDMA SPI1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI1 TX. Software can configure the TX channel setting by SPI1_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 12 - 15 (4 bit)
access : read-write

SPI2_RXSEL : PDMA SPI2 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 RX. Software can configure the RX channel setting by SPI2_RXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 16 - 19 (4 bit)
access : read-write

SPI2_TXSEL : PDMA SPI2 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral SPI2 TX. Software can configure the TX channel setting by SPI2_TXSEL. The channel configuration is the same as SPI0_RXSEL field. Please refer to the explanation of SPI0_RXSEL.
bits : 20 - 23 (4 bit)
access : read-write

UART0_RXSEL : This filed defines which PDMA channel is connected to the on-chip peripheral UART0 RX. Software can change the channel RX setting by UART0_RXSEL.\n4'b0000: CH0\n4'b0001: CH1\n4'b0010: CH2\n4'b0011: CH3 \n4'b0100: CH4 \n4'b0101: CH5\nOthers : Reserved
bits : 0 - 3 (4 bit)
access : read-write

UART0_TXSEL : PDMA UART0 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART0 TX. Software can configure the TX channel setting by UART0_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.
bits : 4 - 7 (4 bit)
access : read-write

UART1_RXSEL : PDMA UART1 RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 RX. Software can configure the RX channel setting by UART1_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.
bits : 8 - 11 (4 bit)
access : read-write

UART1_TXSEL : PDMA UART1 TX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral UART1 TX. Software can configure the TX channel setting by UART1_TXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.
bits : 12 - 15 (4 bit)
access : read-write

ADC_RXSEL : PDMA ADC RX Selection\nThis filed defines which PDMA channel is connected to the on-chip peripheral ADC RX. Software can configure the RX channel setting by ADC_RXSEL. The channel configuration is the same as UART0_RXSEL field. Please refer to the explanation of UART0_RXSEL.
bits : 24 - 27 (4 bit)
access : read-write

INTR0 : Interrupt Pin Status of Channel 0\nThis bit is the Interrupt status of PDMA channel 0.\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-only

INTR1 : Interrupt Pin Status of Channel 1\nThis bit is the Interrupt status of PDMA channel 1.\nNote: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-only

INTR2 : Interrupt Pin Status of Channel 2\nThis bit is the Interrupt status of PDMA channel 2.\nNote: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-only

INTR3 : Interrupt Pin Status of Channel 3\nThis bit is the Interrupt status of PDMA channel 3.\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-only

INTR4 : Interrupt Pin Status of Channel 4\nThis bit is the Interrupt status of PDMA channel 4.\nNote: This bit is read only.
bits : 4 - 4 (1 bit)
access : read-only

INTR5 : Interrupt Pin Status of Channel 5 \nThis bit is the Interrupt status of PDMA channel 5.\nNote: This bit is read only.
bits : 5 - 5 (1 bit)
access : read-only

CRC_INTR : Interrupt Pin Status of CRC Controller\nThis bit is the Interrupt status of CRC controller.\nNote: This bit is read only.
bits : 6 - 6 (1 bit)
access : read-only

INTR : Interrupt Pin Status\nThis bit is the Interrupt status of PDMA controller.\nNote: This bit is read only
bits : 31 - 31 (1 bit)
access : read-only