\n

GCR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xA0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x44 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x30 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xCC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDID

REGWRPROT

BODCR

PORCR

GPA_MFP

GPB_MFP

GPC_MFP

GPD_MFP

RSTSRC

GPF_MFP

ALT_MFP

ALT_MFP1

IPRSTC1

DFP_CSR

IPRSTC2

GPA_IOCR

GPB_IOCR

GPD_IOCR


PDID

Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDID PDID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDID

PDID : Part Device Identification Number\nThis register reflects the device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only


REGWRPROT

Register Write Protect register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REGWRPROT REGWRPROT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGPROTDIS REGWRPROT

REGPROTDIS : Register Write-Protection Disable index (Read Only)\nThe Protected registers are:\nIPRSTC1: address 0x5000_0008\nBODCR: address 0x5000_0018\nPORCR: address 0x5000_0024\nPWRCON: address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear) \nAPBCLK bit[0]: address 0x5000_0208 (bit[0] is watchdog clock enabled)\nCLKSEL0: address 0x5000_0210 (for HCLK and CPU STCLK clock source select)\nCLKSEL1 bit[1:0]: address 0x5000_0214 (for watchdog clock source select)\nISPCON: address 0x5000_C000 (Flash ISP Control register)\nWTCR: address 0x4000_4000\nFATCON: address 0x5000_C018
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Write-protection Enabled for writing protected registers. Any write to the protected register is ignored

#1 : 1

Write-protection Disabled for writing protected registers

End of enumeration elements list.

REGWRPROT : Register Write-Protection Code (Write Only) Some registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGPROTDIS bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only


BODCR

Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BODCR BODCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOD_EN BOD_VL BOD_RSTEN BOD_INTF BOD_LPM BOD_OUT LVR_EN

BOD_EN : Brown-out Detector Enable (Write-protection Bit) The default value is set by flash controller user configuration register config0 bit[23]. This bit is the protected bit, which means programming it needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector function Disabled

#1 : 1

Brown-out Detector function Enabled

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Selection (Write-protection Bits)\n
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable (Write-protection Bit) While the BOD function is enabled (BOD_EN high) and BOD interrupt function is enabled (BOD_RSTEN low), BOD will assert an interrupt if BOD_OUT is high. BOD interrupt will keep till to the BOD_EN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BOD_EN low). The default value is set by flash controller user configuration register config0 bit[20]. This bit is the protected bit. It means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out INTERRUPT function Enabled

#1 : 1

Brown-out RESET function Enabled

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\nSoftware can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BOD_VL setting

#1 : 1

When Brown-out Detector detects the VDD is dropped down through the voltage of BOD_VL setting or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to 1 and the Brown-out interrupt is requested if Brown-out interrupt is enabled

End of enumeration elements list.

BOD_LPM : Brown-out Detector Low power Mode (Write-protection Bit) The BOD consumes about 100 uA in Normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

BOD operated in Normal mode (Default)

#1 : 1

BOD low power mode Enabled

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brown-out Detector output status is 0, which means the detected voltage is higher than BOD_VL setting or BOD_EN is 0

#1 : 1

Brown-out Detector output status is 1, which means the detected voltage is lower than BOD_VL setting. If the BOD_EN is 0, BOD function disabled , this bit always responds to 0

End of enumeration elements list.

LVR_EN : Low Voltage Reset Enable (Write-protection Bit) The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default. This bit is the protected bit, which means programming it needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low Voltage Reset function Disabled

#1 : 1

Low Voltage Reset function Enabled- After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (Default)

End of enumeration elements list.


PORCR

Power-On-Reset Controller Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PORCR PORCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POR_DIS_CODE

POR_DIS_CODE : The register is used for the Power-On-Reset enable control (Write-protection Bits) When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will become active again when this field is set to another value or chip is reset by other reset source, including: /RESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function This bit is the protected bit, which means programming it needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write


GPA_MFP

GPIOA Multiple Function and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPA_MFP GPA_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPA_MFP10 GPA_MFP11 GPA_MFP12 GPA_MFP13 GPA_MFP14 GPA_MFP15 GPA_TYPEn

GPA_MFP10 : PA.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPA_MFP11 : PA.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

GPA_MFP12 : PA.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPA_MFP13 : PA.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPA_MFP14 : PA.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPA_MFP15 : PA.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPA_TYPEn : GPA[9:0] are reserved in this chip.
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOA[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOA[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPB_MFP

GPIOB Multiple Function and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPB_MFP GPB_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPB_MFP0 GPB_MFP1 GPB_MFP2 GPB_MFP3 GPB_MFP4 GPB_MFP5 GPB_MFP6 GPB_MFP7 GPB_MFP8 GPB_MFP9 GPB_MFP10 GPB_MFP12 GPB_MFP13 GPB_MFP14 GPB_MFP15 GPB_TYPEn

GPB_MFP0 : PB.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[0] is selected to the pin PB.0

#1 : 1

UART0 RXD0 function is selected to the pin PB.0

End of enumeration elements list.

GPB_MFP1 : PB.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB[1] is selected to the pin PB.1

#1 : 1

UART0 TXD0 function is selected to the pin PB.1

End of enumeration elements list.

GPB_MFP2 : PB.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPB_MFP3 : PB.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPB_MFP4 : PB.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

GPB_MFP5 : PB.
bits : 5 - 5 (1 bit)
access : read-write

GPB_MFP6 : PB.6 Pin Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

GPB_MFP7 : PB.7 Pin Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

GPB_MFP8 : PB.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

GPB_MFP9 : PB.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

GPB_MFP10 : PB.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

GPB_MFP12 : PB.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPB_MFP13 : PB.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPB_MFP14 : PB.14 Pin Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

GPB_MFP15 : PB.15 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

GPB_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOB[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOB[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPC_MFP

GPIOC Multiple Function and Input Type Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPC_MFP GPC_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPC_MFP0 GPC_MFP1 GPC_MFP2 GPC_MFP3 GPC_MFP4 GPC_MFP5 GPC_MFP8 GPC_MFP9 GPC_MFP10 GPC_MFP11 GPC_MFP12 GPC_MFP13 GPC_TYPEn

GPC_MFP0 : PC.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

GPC_MFP1 : PC.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPC_MFP2 : PC.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPC_MFP3 : PC.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPC_MFP4 : PC.4 Pin Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

GPC_MFP5 : PC.5 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

GPC_MFP8 : PC.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

GPC_MFP9 : PC.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[9] is selected to the pin PC.9

#1 : 1

SPICLK1 (SPI1) function is selected to the pin PC.9

End of enumeration elements list.

GPC_MFP10 : PC.10 Pin Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The GPIOC[10] is selected to the pin PC.10

#1 : 1

MISO10 (SPI1 master input, slave output pin-0) function is selected to the pin PC.10

End of enumeration elements list.

GPC_MFP11 : PC.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOC[11] is selected to the pin PC.11

#1 : 1

MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PC.11

End of enumeration elements list.

GPC_MFP12 : PC.12 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

GPC_MFP13 : PC.13 Pin Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

GPC_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOC[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOC[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


GPD_MFP

GPIOD Multiple Function and Input Type Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPD_MFP GPD_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD_MFP0 GPD_MFP1 GPD_MFP2 GPD_MFP3 GPD_MFP4 GPD_MFP5 GPD_MFP8 GPD_MFP9 GPD_MFP10 GPD_MFP11 GPD_TYPEn

GPD_MFP0 : PD.0 Pin Function Selection \n
bits : 0 - 0 (1 bit)
access : read-write

GPD_MFP1 : PD.1 Pin Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

GPD_MFP2 : PD.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPD_MFP3 : PD.3 Pin Function Selection\n
bits : 3 - 3 (1 bit)
access : read-write

GPD_MFP4 : PD.4 Pin Function Selection \n
bits : 4 - 4 (1 bit)
access : read-write

GPD_MFP5 : PD.5 Pin Function Selection \n
bits : 5 - 5 (1 bit)
access : read-write

GPD_MFP8 : PD.8 Pin Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[8] is selected to the pin PD8

#1 : 1

MOSI10 (SPI1 master output, slave input pin-0) function is selected to the pin PD8

End of enumeration elements list.

GPD_MFP9 : PD.9 Pin Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

GPD_MFP10 : PD.10 Pin Function Selection \n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[10] is selected to the pin PD.10

#1 : 1

CLKO function is selected to the pin PD.10

End of enumeration elements list.

GPD_MFP11 : PD.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOD[11] is selected to the pin PD.11

#1 : 1

/INT1 function is selected to the pin PD.11

End of enumeration elements list.

GPD_TYPEn : None
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIOD[15:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOD[15:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


RSTSRC

System Reset Source Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSRC RSTSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTS_POR RSTS_RESET RSTS_WDT RSTS_LVR RSTS_BOD RSTS_SYS RSTS_CPU

RSTS_POR : The RSTS_POR flag is set by the reset signal from the Power-On Reset (POR) controller or bit CHIP_RST (IPRSTC1[0]) to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from POR or CHIP_RST

#1 : 1

Power-On Reset (POR) or CHIP_RST had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_RESET : The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from /RESET pin

#1 : 1

Pin /RESET had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_WDT : The RSTS_WDT flag is set by the reset signal from the watchdog timer to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from watchdog timer

#1 : 1

Watchdog timer had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_LVR : The RSTS_LVR flag is set by the reset signal from the Low-Voltage-Reset controller to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from LVR

#1 : 1

LVR controller had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_BOD : The RSTS_BOD flag is set by the reset signal from the Brown-out-Detector to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from BOD

#1 : 1

BOD had issued the reset signal to reset the system

End of enumeration elements list.

RSTS_SYS : The RSTS_SYS flag is set by the reset signal from the Cortex_M0 kernel to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from Cortex_M0

#1 : 1

Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex_M0 kernel

End of enumeration elements list.

RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).\nSoftware can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CPU

#1 : 1

Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1

End of enumeration elements list.


GPF_MFP

GPIOF Multiple Function and Input Type Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPF_MFP GPF_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPF_MFP0 GPF_MFP1 GPF_MFP2 GPF_MFP3 GPF_TYPEn

GPF_MFP0 : PF.0 Pin Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOF[0] is selected to the pin PF.0

#1 : 1

XT1_OUT function is selected to the pin PF.0

End of enumeration elements list.

GPF_MFP1 : PF.1 Pin Function Selection \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOF[1] is selected to the pin PF.1

#1 : 1

XT1_IN function is selected to the pin PF.1

End of enumeration elements list.

GPF_MFP2 : PF.2 Pin Function Selection\n
bits : 2 - 2 (1 bit)
access : read-write

GPF_MFP3 : PF.3 Pin Function Selection \n
bits : 3 - 3 (1 bit)
access : read-write

GPF_TYPEn : None
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

0 : 0

GPIOF[3:0] I/O input Schmitt Trigger function Disabled

1 : 1

GPIOF[3:0] I/O input Schmitt Trigger function Enabled

End of enumeration elements list.


ALT_MFP

Alternative Multiple Function Pin Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALT_MFP ALT_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB10_MFP1 PB9_MFP1 PC0_MFP1 PC1_MFP1 PC2_MFP1 PC3_MFP1 PA15_MFP1 PB12_MFP1 PA11_MFP1 PA10_MFP1 PB4_MFP1 PB7_MFP1 PB6_MFP1 PB5_MFP1 PC12_MFP1 PC13_MFP1 PB15_MFP1 PB2_MFP1 PB3_MFP1 PC4_MFP1 PC5_MFP1

PB10_MFP1 : PB.10 Pin Alternate Function Selection\n
bits : 0 - 0 (1 bit)
access : read-write

PB9_MFP1 : PB.9 Pin Alternate Function Selection\n
bits : 1 - 1 (1 bit)
access : read-write

PC0_MFP1 : PC.0 Pin Function Selection\n
bits : 5 - 5 (1 bit)
access : read-write

PC1_MFP1 : PC.1 Pin Alternate Function Selection\n
bits : 6 - 6 (1 bit)
access : read-write

PC2_MFP1 : PC.2 Pin Alternate Function Selection\n
bits : 7 - 7 (1 bit)
access : read-write

PC3_MFP1 : PC.3 Pin Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

PA15_MFP1 : PA.15 Pin Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

PB12_MFP1 : PB.12 Pin Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

PA11_MFP1 : PA.11 Pin Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

PA10_MFP1 : PA.10 Pin Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

PB4_MFP1 : PB.4 Pin Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

PB7_MFP1 : PB.7 Pin Alternate Function Selection\n
bits : 16 - 16 (1 bit)
access : read-write

PB6_MFP1 : PB.6 Pin Alternate Function Selection\n
bits : 17 - 17 (1 bit)
access : read-write

PB5_MFP1 : PB.
bits : 18 - 18 (1 bit)
access : read-write

PC12_MFP1 : PC.12 Pin Function Selection\n
bits : 20 - 20 (1 bit)
access : read-write

PC13_MFP1 : PC.13 Pin Function Selection\n
bits : 21 - 21 (1 bit)
access : read-write

PB15_MFP1 : PB.15 Pin Alternate Function Selection\n
bits : 24 - 24 (1 bit)
access : read-write

PB2_MFP1 : PB.2 Pin Alternate Function Selection\n
bits : 26 - 26 (1 bit)
access : read-write

PB3_MFP1 : PB.3 Pin Alternate Function Selection\n
bits : 27 - 27 (1 bit)
access : read-write

PC4_MFP1 : PC.4 Pin Function Selection\n
bits : 29 - 29 (1 bit)
access : read-write

PC5_MFP1 : PC.5 Pin Function Selection\n
bits : 30 - 30 (1 bit)
access : read-write


ALT_MFP1

Alternative Multiple Function Pin Control Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALT_MFP1 ALT_MFP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0_MFP1 PD1_MFP1 PD2_MFP1 PD3_MFP1 PD4_MFP1 PD5_MFP1 PF2_MFP1 PF3_MFP1

PD0_MFP1 : PD.0 Pin Function Selection \n
bits : 16 - 16 (1 bit)
access : read-write

PD1_MFP1 : PD.1 Pin Function Selection\n
bits : 17 - 17 (1 bit)
access : read-write

PD2_MFP1 : PD.2 Pin Function Selection\n
bits : 18 - 18 (1 bit)
access : read-write

PD3_MFP1 : PD.3 Pin Function Selection\n
bits : 19 - 19 (1 bit)
access : read-write

PD4_MFP1 : PD.4 Pin Function Selection \n
bits : 20 - 20 (1 bit)
access : read-write

PD5_MFP1 : PD.5 Pin Function Selection \n
bits : 21 - 21 (1 bit)
access : read-write

PF2_MFP1 : PF.2 Pin Function Selection\n
bits : 24 - 25 (2 bit)
access : read-write

PF3_MFP1 : PF.3 Pin Function Selection \n
bits : 26 - 27 (2 bit)
access : read-write


IPRSTC1

IP Reset Control Register1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRSTC1 IPRSTC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_RST CPU_RST PDMA_RST

CHIP_RST : CHIP One-shot Reset (Write-protection Bit) Setting this bit will reset the whole chip, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. The CHIP_RST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. For the difference between CHIP_RST and SYSRESETREQ, please refer to section 5.2.2. This bit is the protected bit, which means programming it needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

CHIP normal operation

#1 : 1

CHIP one-shot reset

End of enumeration elements list.

CPU_RST : CPU kernel one-shot reset (Write-protection Bit) Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

CPU normal operation

#1 : 1

CPU one-shot reset

End of enumeration elements list.

PDMA_RST : PDMA Controller Reset (Write-protection) Setting this bit to 1 will generate a reset signal to the PDMA. User need to set this bit to 0 to release from reset state. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA controller normal operation

#1 : 1

PDMA controller reset

End of enumeration elements list.


DFP_CSR

Pin Conflict Status
address_offset : 0xA0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DFP_CSR DFP_CSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFP0_CST DFP1_CST DFP2_CST DFP3_CST DFP4_CST DFP5_CST DFP6_CST

DFP0_CST : Conflict Status of PD.9\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

PD.9 worked normally

#1 : 1

PD.9 is conflicted

End of enumeration elements list.

DFP1_CST : Conflict Status of PD.10\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

PD.10 worked normally

#1 : 1

PD.10 is conflicted

End of enumeration elements list.

DFP2_CST : Conflict Status of PD.11\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

PD.11 worked normally

#1 : 1

PD.11 is conflicted

End of enumeration elements list.

DFP3_CST : Conflict Status of PB.4\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

PB.4 worked normally

#1 : 1

PB.4 is conflicted

End of enumeration elements list.

DFP4_CST : Conflict Status of PB.5\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

PB.5 worked normally

#1 : 1

PB.5 is conflicted

End of enumeration elements list.

DFP5_CST : Conflict Status of PB.6\n
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

PB.6 worked normally

#1 : 1

PB.6 is conflicted

End of enumeration elements list.

DFP6_CST : Conflict Status of PB.7\n
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

PB.7 worked normally

#1 : 1

PB.7 is conflicted

End of enumeration elements list.


IPRSTC2

IP Reset Control Register2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPRSTC2 IPRSTC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO_RST TMR0_RST TMR1_RST TMR2_RST TMR3_RST I2C0_RST I2C1_RST SPI0_RST SPI1_RST SPI2_RST UART0_RST UART1_RST PWM03_RST PS2_RST USBD_RST ADC_RST I2S_RST

GPIO_RST : GPIO controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO controller normal operation

#1 : 1

GPIO controller reset

End of enumeration elements list.

TMR0_RST : Timer0 controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 controller normal operation

#1 : 1

Timer0 controller reset

End of enumeration elements list.

TMR1_RST : Timer1 controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 controller normal operation

#1 : 1

Timer1 controller reset

End of enumeration elements list.

TMR2_RST : Timer2 controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 controller normal operation

#1 : 1

Timer2 controller reset

End of enumeration elements list.

TMR3_RST : Timer3 controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 controller normal operation

#1 : 1

Timer3 controller reset

End of enumeration elements list.

I2C0_RST : I2C0 controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 controller normal operation

#1 : 1

I2C0 controller reset

End of enumeration elements list.

I2C1_RST : I2C1 controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 controller normal operation

#1 : 1

I2C1 controller reset

End of enumeration elements list.

SPI0_RST : SPI0 controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 controller normal operation

#1 : 1

SPI0 controller reset

End of enumeration elements list.

SPI1_RST : SPI1 controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 controller normal operation

#1 : 1

SPI1 controller reset

End of enumeration elements list.

SPI2_RST : SPI2 controller Reset \n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 controller normal operation

#1 : 1

SPI2 controller reset

End of enumeration elements list.

UART0_RST : UART0 controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 controller normal operation

#1 : 1

UART0 controller reset

End of enumeration elements list.

UART1_RST : UART1 controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 controller normal operation

#1 : 1

UART1 controller reset

End of enumeration elements list.

PWM03_RST : PWM03 controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM03 controller normal operation

#1 : 1

PWM03 controller reset

End of enumeration elements list.

PS2_RST : PS/2 Controller Reset\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PS/2 controller normal operation

#1 : 1

PS/2 controller reset

End of enumeration elements list.

USBD_RST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB device controller normal operation

#1 : 1

USB device controller reset

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC controller normal operation

#1 : 1

ADC controller reset

End of enumeration elements list.

I2S_RST : I2S Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S controller normal operation

#1 : 1

I2S controller reset

End of enumeration elements list.


GPA_IOCR

GPIOA IO Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPA_IOCR GPA_IOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPA10_DS GPA11_DS

GPA10_DS : PA.10 Pin Driving Strength Selection\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PA.10 strong driving strength mode Disabled

#1 : 1

PA.10 strong driving strength mode Enabled

End of enumeration elements list.

GPA11_DS : PA.11 Pin Driving Strength Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PA.11 strong driving strength mode Disabled

#1 : 1

PA.11 strong driving strength mode Enabled

End of enumeration elements list.


GPB_IOCR

GPIOB IO Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPB_IOCR GPB_IOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPB4_DS GPB5_DS GPB6_DS GPB7_DS GPB8_DS GPB12_DS GPB13_DS GPB14_DS

GPB4_DS : PB.4 Pin Driving Strength Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.4 strong driving strength mode Disabled

#1 : 1

PB.4 strong driving strength mode Enabled

End of enumeration elements list.

GPB5_DS : PB.5 Pin Driving Strength Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.5 strong driving strength mode Disabled

#1 : 1

PB.5 strong driving strength mode Enabled

End of enumeration elements list.

GPB6_DS : PB.6 Pin Driving Strength Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.6 strong driving strength mode Disabled

#1 : 1

PB.6 strong driving strength mode Enabled

End of enumeration elements list.

GPB7_DS : PB.7 Pin Driving Strength Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.7 strong driving strength mode Disabled

#1 : 1

PB.7 strong driving strength mode Enabled

End of enumeration elements list.

GPB8_DS : PB.8 Pin Driving Strength Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.8 strong driving strength mode Disabled

#1 : 1

PB.8 strong driving strength mode Enabled

End of enumeration elements list.

GPB12_DS : PB.12 Pin Driving Strength Selection\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.12 strong driving strength mode Disabled

#1 : 1

PB.12 strong driving strength mode Enabled

End of enumeration elements list.

GPB13_DS : PB.13 Pin Driving Strength Selection\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.13 strong driving strength mode Disabled

#1 : 1

PB.13 strong driving strength mode Enabled

End of enumeration elements list.

GPB14_DS : PB.14 Pin Driving Strength Selection\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PB.14 strong driving strength mode Disabled

#1 : 1

PB.14 strong driving strength mode Enabled

End of enumeration elements list.


GPD_IOCR

GPIOD IO Control Register
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPD_IOCR GPD_IOCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPD8_DS GPD9_DS GPD10_DS GPD11_DS

GPD8_DS : PD.8 Pin Driving Strength Selection\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PD.8 strong driving strength mode Disabled

#1 : 1

PD.8 strong driving strength mode Enabled

End of enumeration elements list.

GPD9_DS : PD.9 Pin Driving Strength Selection\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PD.9 strong driving strength mode Disabled

#1 : 1

PD.9 strong driving strength mode Enabled

End of enumeration elements list.

GPD10_DS : PD.10 Pin Driving Strength Selection\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PD.10 strong driving strength mode Disabled

#1 : 1

PD.10 strong driving strength mode Enabled

End of enumeration elements list.

GPD11_DS : PD.11 Pin Driving Strength Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PD.11 strong driving strength mode Disabled

#1 : 1

PD.11 strong driving strength mode Enabled

End of enumeration elements list.



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