ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPDAT

ISPCMD

ISPEN : ISP Enable (Write-protection Bit)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write-protection Bit)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable (Write-protection Bit)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config-bits Update by ISP (Write-protection Bit)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable (Write-protection Bit)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write-protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nWrite 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nWhen DFVSEN is set to 0, the data flash is shared with APROM. The data flash size is defined by user configuration and the content of this register is loaded from Config1.\nWhen DFVSEN is set to 1, the data flash size is fixed as 4K and the start address can be read from this register is fixed at 0x0001_F000.
bits : 0 - 31 (32 bit)
access : read-only

LFOM : Low Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 25 MHz, chip can work more efficiently by setting this bit to 1\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MFOM : Middle Frequency Optimization Mode (Write-protection Bit)\nWhen chip operation frequency is lower than 50 MHz, chip can work more efficiently by setting this bit to 1\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADR : ISP Address\nThe NuMicro( NUC123 Series is equipped with an embedded flash, and it supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPCMD : ISP Command\n
bits : 0 - 5 (6 bit)
access : read-write