\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x500 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
USB Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_IE : Bus Event Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BUS event interrupt Disabled
#1 : 1
BUS event interrupt Enabled
End of enumeration elements list.
USB_IE : USB Event Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB event interrupt Disabled
#1 : 1
USB event interrupt Enabled
End of enumeration elements list.
FLDET_IE : Floating Detected Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Floating detect Interrupt Disabled
#1 : 1
Floating detect Interrupt Enabled
End of enumeration elements list.
WAKEUP_IE : USB Wake-up Interrupt Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up Interrupt Disabled
#1 : 1
Wake-up Interrupt Enabled
End of enumeration elements list.
WAKEUP_EN : Wake-up Function Enable\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB wake-up function Disabled
#1 : 1
USB wake-up function Enabled
End of enumeration elements list.
INNAK_EN : Active NAK Function and its Status in IN Token\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
NAK status wasn't updated into the endpoint status register when it was set to 0. It also disables the interrupt event when device responds NAK after receiving IN token
#1 : 1
NAK status is updated into the endpoint status register, USB_EPSTS, when it is set to 1 and there is NAK response in IN token. It also enables the interrupt event when the device responds NAK after receiving IN token
End of enumeration elements list.
USB Bus Status and Attribution Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBRST : USB Reset Status\nIt is a read only bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus reset
#1 : 1
Bus reset when SE0 (single-ended 0) more than 2.5 us
End of enumeration elements list.
SUSPEND : Suspend Status\nIt is a read only bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus suspend
#1 : 1
Bus idle more than 3ms, either cable is plugged off or host is sleeping
End of enumeration elements list.
RESUME : Resume Status\nIt is a read only bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus resume
#1 : 1
Resume from suspend
End of enumeration elements list.
TIME_OUT : Time Out Status\nIt is a read only bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No time-out
#1 : 1
No Bus response more than 18 bits time
End of enumeration elements list.
PHY_EN : PHY Transceiver Function Enable\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PHY transceiver function Disabled
#1 : 1
PHY transceiver function Enabled
End of enumeration elements list.
RWAKEUP : Remote Wake-up\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Release the USB bus from K state
#1 : 1
Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up
End of enumeration elements list.
USB_EN : USB Controller Enable\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Controller Disabled
#1 : 1
USB Controller Enabled
End of enumeration elements list.
DPPU_EN : Pull-up resistor on USB_DP enable\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
the pull-up resistor in USB_DP bus Disabled
#1 : 1
Pull-up resistor in USB_DP bus Enabled
End of enumeration elements list.
PWRDN : Power-down PHY Transceiver, Low Active\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down related circuit of PHY transceiver
#1 : 1
Turn-on related circuit of PHY transceiver
End of enumeration elements list.
BYTEM : CPU access USB SRAM Size Mode Selection\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word Mode: The size of the transfer from CPU to USB SRAM can be Word only
#1 : 1
Byte Mode: The size of the transfer from CPU to USB SRAM can be Byte only
End of enumeration elements list.
USB Floating Detected Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FLDET : Device Floating Detected\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Controller isn't attached to the USB host
#1 : 1
Controller is attached to the BUS
End of enumeration elements list.
Setup Token Buffer Segmentation Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEG : It is used to indicate the offset address for the Setup token with the USB SRAM starting address. The effective starting address is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000} \nNote: It is used for Setup token only.
bits : 3 - 8 (6 bit)
access : read-write
USB Interrupt Event Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_STS : BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No BUS event occurred
#1 : 1
Bus event occurred check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USB_INTSTS[0]
End of enumeration elements list.
USB_STS : USB event Interrupt Status\nThe USB event includes the Setup Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No USB event occurred
#1 : 1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[1] or EPSTS0~5 and SETUP (USB_INTSTS[31])
End of enumeration elements list.
FLDET_STS : Floating Detected Interrupt Status\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is not attached/detached event in the USB
#1 : 1
There is attached/detached event in the USB bus and it is cleared by writing 1 to USB_INTSTS[2]
End of enumeration elements list.
WAKEUP_STS : Wake-up Interrupt Status\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Wake-up event occurred
#1 : 1
Wake-up event occurred, cleared by writing 1 to USB_INTSTS[3]
End of enumeration elements list.
EPEVT0 : Endpoint 0's USB Event Status\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 0
#1 : 1
USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[16] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT1 : Endpoint 1's USB Event Status\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 1
#1 : 1
USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[17] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT2 : Endpoint 2's USB Event Status\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 2
#1 : 1
USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[18] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT3 : Endpoint 3's USB Event Status\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 3
#1 : 1
USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[19] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT4 : Endpoint 4's USB Event Status\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 4
#1 : 1
USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[20] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT5 : Endpoint 5's USB Event Status\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 5
#1 : 1
USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[21] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT6 : Endpoint 6's USB Event Status\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred on Endpoint 6
#1 : 1
USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[22] or USB_INTSTS[1]
End of enumeration elements list.
EPEVT7 : Endpoint 7's USB Event Status\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 7
#1 : 1
USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by writing 1 to USB_INTSTS[23] or USB_INTSTS[1]
End of enumeration elements list.
SETUP : Setup Event Status\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Setup event
#1 : 1
Setup event occurred, and cleared by writing 1 to USB_INTSTS[31]
End of enumeration elements list.
Endpoint 0 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEGx : It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:\nUSB_SRAM address + { BUFSEG[8:3], 3'b000}\nRefer to section 5.4.4.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write
Endpoint 0 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPLD : Maximal Payload
It is used to define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It is also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD indicates the data length be transmitted to host
For OUT token, the value of MXPLD indicates the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write
Endpoint 0 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_NUM : Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint.
bits : 0 - 3 (4 bit)
access : read-write
ISOCH : Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Isochronous endpoint
#1 : 1
Isochronous endpoint
End of enumeration elements list.
STATE : Endpoint STATE\n
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 0
Endpoint Disabled
#01 : 1
Out endpoint
#10 : 2
IN endpoint
#11 : 3
Undefined
End of enumeration elements list.
DSQ_SYNC : Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the following IN token transaction. H/W will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DATA0 PID
#1 : 1
DATA1 PID
End of enumeration elements list.
CSTALL : Clear STALL Response\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Device Disabled to clear the STALL handshake in the setup stage
#1 : 1
Clear the device to respond STALL handshake in the setup stage
End of enumeration elements list.
Endpoint 0 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRRDY : Clear Ready\nWhen the MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to turn off this transaction before the transaction start, user can set this bit to 1 to turn it off and it is automatically cleared to 0.\nFor IN token, writing '1' is used to clear the IN token had ready to transmit the data to USB.\nFor OUT token, writing '1' is used to clear the OUT token had ready to receive the data from USB.\nThis bit is written 1 only and is always 0 when it was read back.
bits : 0 - 0 (1 bit)
access : read-write
SSTALL : Set STALL\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Device Disabled to respond STALL
#1 : 1
Set the device to respond STALL automatically
End of enumeration elements list.
Endpoint 1 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x54C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x550 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x554 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x558 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x55C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 6 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x560 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 6 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x564 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 6 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 6 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x56C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 7 Buffer Segmentation Register. It is also mirrored to USB_BA+0x020 for backward compatible.
address_offset : 0x570 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 7 Maximal Payload Register. It is also mirrored to USB_BA+0x024 for backward compatible.
address_offset : 0x574 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 7 Configuration Register. It is also mirrored to USB_BA+0x028 for backward compatible.
address_offset : 0x578 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 7 Set Stall and Clear In/Out Ready Control Register. It is also mirrored to USB_BA+0x02C for backward compatible.
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Device Function Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADDR : USB device's Function Address
bits : 0 - 6 (7 bit)
access : read-write
USB Drive SE0 Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DRVSE0 : Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_DP and USB_DM) are being pulled low.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
None
#1 : 1
Force USB PHY transceiver to drive SE0
End of enumeration elements list.
USB PDMA Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_RW : PDMA_RW\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PDMA will read data from memory to USB buffer
#1 : 1
The PDMA will read data from USB buffer to memory
End of enumeration elements list.
PDMA_EN : PDMA Function Enable\nThis bit will be automatically cleared after PDMA transfer done.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PDMA function is not active
#1 : 1
The PDMA function in USB is active
End of enumeration elements list.
USB Endpoint Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVERRUN : Overrun\nIt indicates that the received data is over the maximum payload number or not.\n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun
#1 : 1
Out data is more than the Max Payload in MXPLD register or the Setup data is more than 8 Bytes
End of enumeration elements list.
EPSTS0 : Endpoint 0 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS1 : Endpoint 1 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 11 - 13 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS2 : Endpoint 2 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 14 - 16 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS3 : Endpoint 3 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS4 : Endpoint 4 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 20 - 22 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS5 : Endpoint 5 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 23 - 25 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS6 : Endpoint 6 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 26 - 28 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS7 : Endpoint 7 Bus Status\nThese bits are used to indicate the current status of this endpoint.\n
bits : 29 - 31 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
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