\n

GP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x140 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x340 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x228 Bytes (0x0)
size : 0x90 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x2C0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GPIOA_PMD

GPIOA_PIN

GPIOA_DBEN

GPIOF_PMD

GPIOF_OFFD

GPIOF_DOUT

GPIOF_DMASK

GPIOF_PIN

GPIOF_DBEN

GPIOF_IMD

GPIOF_IEN

GPIOF_ISRC

GPIOA_IMD

DBNCECON

GPIOA_IEN

GPIOA_ISRC

PA10_PDIO

PA11_PDIO

PA12_PDIO

PA13_PDIO

PA14_PDIO

PA15_PDIO

PB0_PDIO

PB1_PDIO

PB2_PDIO

PB3_PDIO

PB4_PDIO

PB5_PDIO

PB6_PDIO

PB7_PDIO

PB8_PDIO

PB9_PDIO

PB10_PDIO

PB11_PDIO

PB12_PDIO

PB13_PDIO

PB14_PDIO

PB15_PDIO

PC0_PDIO

PC1_PDIO

PC2_PDIO

PC3_PDIO

PC4_PDIO

PC5_PDIO

PC6_PDIO

PC7_PDIO

PC8_PDIO

PC9_PDIO

PC10_PDIO

PC11_PDIO

PC12_PDIO

PC13_PDIO

PD0_PDIO

PD1_PDIO

PD2_PDIO

PD3_PDIO

PD4_PDIO

PD5_PDIO

PD6_PDIO

PD7_PDIO

PD8_PDIO

PD9_PDIO

PD10_PDIO

PD11_PDIO

PF0_PDIO

PF1_PDIO

PF2_PDIO

PF3_PDIO

GPIOA_OFFD

GPIOB_PMD

GPIOB_OFFD

GPIOB_DOUT

GPIOB_DMASK

GPIOB_PIN

GPIOB_DBEN

GPIOB_IMD

GPIOB_IEN

GPIOB_ISRC

GPIOA_DOUT

GPIOC_PMD

GPIOC_OFFD

GPIOC_DOUT

GPIOC_DMASK

GPIOC_PIN

GPIOC_DBEN

GPIOC_IMD

GPIOC_IEN

GPIOC_ISRC

GPIOA_DMASK

GPIOD_PMD

GPIOD_OFFD

GPIOD_DOUT

GPIOD_DMASK

GPIOD_PIN

GPIOD_DBEN

GPIOD_IMD

GPIOD_IEN

GPIOD_ISRC


GPIOA_PMD

GPIO Port A Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PMD GPIOA_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15

PMD10 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD11 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD12 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD13 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD14 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD15 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


GPIOA_PIN

GPIO Port A Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOA_PIN GPIOA_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN10 PIN11 PIN12 PIN13 PIN14 PIN15

PIN10 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-only


GPIOA_DBEN

GPIO Port A De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DBEN GPIOA_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN10 DBEN11 DBEN12 DBEN13 DBEN14 DBEN15

DBEN10 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN11 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN12 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN13 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN14 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN15 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


GPIOF_PMD

GPIO Port F Pin I/O Mode Control
address_offset : 0x140 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_PMD GPIOF_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3

PMD0 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


GPIOF_OFFD

GPIO Port F Pin OFF Digital Enable
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_OFFD GPIOF_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD0 OFFD1 OFFD2 OFFD3

OFFD0 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD1 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD2 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD3 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.


GPIOF_DOUT

GPIO Port F Data Output Value
address_offset : 0x148 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DOUT GPIOF_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT0 DOUT1 DOUT2 DOUT3

DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.


GPIOF_DMASK

GPIO Port F Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DMASK GPIOF_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK0 DMASK1 DMASK2 DMASK3

DMASK0 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.


GPIOF_PIN

GPIO Port F Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOF_PIN GPIOF_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN0 PIN1 PIN2 PIN3

PIN0 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-only


GPIOF_DBEN

GPIO Port F De-bounce Enable
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_DBEN GPIOF_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN0 DBEN1 DBEN2 DBEN3

DBEN0 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


GPIOF_IMD

GPIO Port F Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_IMD GPIOF_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD0 IMD1 IMD2 IMD3

IMD0 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.


GPIOF_IEN

GPIO Port F Interrupt Enable
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_IEN GPIOF_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN0 IF_EN1 IF_EN2 IF_EN3 IR_EN0 IR_EN1 IR_EN2 IR_EN3

IF_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.


GPIOF_ISRC

GPIO Port F Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOF_ISRC GPIOF_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC0 ISRC1 ISRC2 ISRC3

ISRC0 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.


GPIOA_IMD

GPIO Port A Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_IMD GPIOA_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD10 IMD11 IMD12 IMD13 IMD14 IMD15

IMD10 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD11 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD12 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD13 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD14 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD15 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.


DBNCECON

De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBNCECON DBNCECON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBCLKSEL DBCLKSRC ICLK_ON

DBCLKSEL : De-bounce sampling cycle selection\n
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce counter clock source select\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the internal 10 kHz low speed oscillator

End of enumeration elements list.

ICLK_ON : Interrupt clock On mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock Disabled if the GPIOA/B/C/D/F[n] interrupt is disabled

#1 : 1

Interrupt generated circuit clock always Enabled

End of enumeration elements list.


GPIOA_IEN

GPIO Port A Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_IEN GPIOA_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN10 IF_EN11 IF_EN12 IF_EN13 IF_EN14 IF_EN15 IR_EN10 IR_EN11 IR_EN12 IR_EN13 IR_EN14 IR_EN15

IF_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN14 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN15 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN14 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN15 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.


GPIOA_ISRC

GPIO Port A Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_ISRC GPIOA_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC10 ISRC11 ISRC12 ISRC13 ISRC14 ISRC15

ISRC10 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC11 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC12 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC13 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC14 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC15 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.


PA10_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA10_PDIO PA10_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIOxx_DOUT

GPIOxx_DOUT : GPIOxx I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\nRead this register to get IO pin status.\nFor example: Writing GPIOA0_DOUT will reflect the written value to bit GPIOA_DOUT[0], read GPIOA0_DOUT will return the value of GPIOA_PIN[0]
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Set the corresponding GPIO pin to low

#1 : 1

Set the corresponding GPIO pin to high

End of enumeration elements list.


PA11_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA11_PDIO PA11_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA12_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA12_PDIO PA12_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA13_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA13_PDIO PA13_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA14_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA14_PDIO PA14_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA15_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA15_PDIO PA15_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB0_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB0_PDIO PB0_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB1_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB1_PDIO PB1_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB2_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB2_PDIO PB2_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB3_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB3_PDIO PB3_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB4_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB4_PDIO PB4_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB5_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB5_PDIO PB5_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB6_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB6_PDIO PB6_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB7_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB7_PDIO PB7_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB8_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB8_PDIO PB8_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB9_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB9_PDIO PB9_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB10_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB10_PDIO PB10_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB11_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB11_PDIO PB11_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB12_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB12_PDIO PB12_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB13_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB13_PDIO PB13_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB14_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB14_PDIO PB14_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB15_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB15_PDIO PB15_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC0_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC0_PDIO PC0_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC1_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC1_PDIO PC1_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC2_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC2_PDIO PC2_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC3_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC3_PDIO PC3_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC4_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC4_PDIO PC4_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC5_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC5_PDIO PC5_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC6_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC6_PDIO PC6_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC7_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC7_PDIO PC7_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC8_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC8_PDIO PC8_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC9_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC9_PDIO PC9_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC10_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC10_PDIO PC10_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC11_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC11_PDIO PC11_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC12_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC12_PDIO PC12_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PC13_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC13_PDIO PC13_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD0_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD0_PDIO PD0_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD1_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1_PDIO PD1_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD2_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD2_PDIO PD2_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD3_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD3_PDIO PD3_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD4_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD4_PDIO PD4_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD5_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD5_PDIO PD5_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD6_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD6_PDIO PD6_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD7_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD7_PDIO PD7_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD8_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD8_PDIO PD8_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD9_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD9_PDIO PD9_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD10_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD10_PDIO PD10_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PD11_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD11_PDIO PD11_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PF0_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF0_PDIO PF0_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PF1_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF1_PDIO PF1_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PF2_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF2_PDIO PF2_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PF3_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF3_PDIO PF3_PDIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOA_OFFD

GPIO Port A Pin OFF Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_OFFD GPIOA_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD10 OFFD11 OFFD12 OFFD13 OFFD14 OFFD15

OFFD10 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD11 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD12 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD13 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD14 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD15 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.


GPIOB_PMD

GPIO Port B Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_PMD GPIOB_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD12 PMD13 PMD14 PMD15

PMD0 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD4 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD5 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD6 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD7 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD8 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD9 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD10 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD12 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD13 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD14 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD15 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


GPIOB_OFFD

GPIO Port B Pin OFF Digital Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_OFFD GPIOB_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD0 OFFD1 OFFD2 OFFD3 OFFD4 OFFD5 OFFD6 OFFD7 OFFD8 OFFD9 OFFD10 OFFD12 OFFD13 OFFD14 OFFD15

OFFD0 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD1 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD2 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD3 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD4 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD5 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD6 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD7 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD8 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD9 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD10 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD12 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD13 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD14 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD15 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.


GPIOB_DOUT

GPIO Port B Data Output Value
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DOUT GPIOB_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DOUT8 DOUT9 DOUT10 DOUT12 DOUT13 DOUT14 DOUT15

DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT4 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT5 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT6 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT7 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT8 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT9 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT12 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT13 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT14 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT15 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.


GPIOB_DMASK

GPIO Port B Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DMASK GPIOB_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK0 DMASK1 DMASK2 DMASK3 DMASK4 DMASK5 DMASK6 DMASK7 DMASK8 DMASK9 DMASK10 DMASK12 DMASK13 DMASK14 DMASK15

DMASK0 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK4 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK5 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK6 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK7 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK8 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK9 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK10 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK12 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK13 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK14 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK15 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.


GPIOB_PIN

GPIO Port B Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOB_PIN GPIOB_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 PIN9 PIN10 PIN12 PIN13 PIN14 PIN15

PIN0 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-only


GPIOB_DBEN

GPIO Port B De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_DBEN GPIOB_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN0 DBEN1 DBEN2 DBEN3 DBEN4 DBEN5 DBEN6 DBEN7 DBEN8 DBEN9 DBEN10 DBEN12 DBEN13 DBEN14 DBEN15

DBEN0 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN4 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN5 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN6 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN7 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN8 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN9 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN10 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN12 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN13 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN14 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN15 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


GPIOB_IMD

GPIO Port B Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IMD GPIOB_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD0 IMD1 IMD2 IMD3 IMD4 IMD5 IMD6 IMD7 IMD8 IMD9 IMD10 IMD12 IMD13 IMD14 IMD15

IMD0 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD6 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD7 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD8 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD9 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD10 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD12 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD13 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD14 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD15 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.


GPIOB_IEN

GPIO Port B Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_IEN GPIOB_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN0 IF_EN1 IF_EN2 IF_EN3 IF_EN4 IF_EN5 IF_EN6 IF_EN7 IF_EN8 IF_EN9 IF_EN10 IF_EN12 IF_EN13 IF_EN14 IF_EN15 IR_EN0 IR_EN1 IR_EN2 IR_EN3 IR_EN4 IR_EN5 IR_EN6 IR_EN7 IR_EN8 IR_EN9 IR_EN10 IR_EN12 IR_EN13 IR_EN14 IR_EN15

IF_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN6 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN7 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN14 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN15 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN6 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN7 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN14 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN15 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.


GPIOB_ISRC

GPIO Port B Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOB_ISRC GPIOB_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC0 ISRC1 ISRC2 ISRC3 ISRC4 ISRC5 ISRC6 ISRC7 ISRC8 ISRC9 ISRC10 ISRC12 ISRC13 ISRC14 ISRC15

ISRC0 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC4 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC5 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC6 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC7 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC8 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC9 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC10 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC12 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC13 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC14 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC15 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.


GPIOA_DOUT

GPIO Port A Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DOUT GPIOA_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15

DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT11 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT12 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT13 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT14 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT15 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.


GPIOC_PMD

GPIO Port C Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_PMD GPIOC_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13

PMD0 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD4 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD5 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD8 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD9 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD10 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD11 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD12 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD13 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


GPIOC_OFFD

GPIO Port C Pin OFF Digital Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_OFFD GPIOC_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD0 OFFD1 OFFD2 OFFD3 OFFD4 OFFD5 OFFD8 OFFD9 OFFD10 OFFD11 OFFD12 OFFD13

OFFD0 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD1 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD2 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD3 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD4 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD5 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD8 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD9 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD10 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD11 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD12 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD13 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.


GPIOC_DOUT

GPIO Port C Data Output Value
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DOUT GPIOC_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13

DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT4 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT5 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT8 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT9 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT11 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT12 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT13 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.


GPIOC_DMASK

GPIO Port C Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DMASK GPIOC_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK0 DMASK1 DMASK2 DMASK3 DMASK4 DMASK5 DMASK8 DMASK9 DMASK10 DMASK11 DMASK12 DMASK13

DMASK0 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK4 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK5 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK8 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK9 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK10 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK11 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK12 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK13 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.


GPIOC_PIN

GPIO Port C Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOC_PIN GPIOC_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN8 PIN9 PIN10 PIN11 PIN12 PIN13

PIN0 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-only


GPIOC_DBEN

GPIO Port C De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_DBEN GPIOC_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN0 DBEN1 DBEN2 DBEN3 DBEN4 DBEN5 DBEN8 DBEN9 DBEN10 DBEN11 DBEN12 DBEN13

DBEN0 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN4 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN5 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN8 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN9 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN10 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN11 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN12 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN13 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


GPIOC_IMD

GPIO Port C Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IMD GPIOC_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD0 IMD1 IMD2 IMD3 IMD4 IMD5 IMD8 IMD9 IMD10 IMD11 IMD12 IMD13

IMD0 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD8 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD9 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD10 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD11 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD12 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD13 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.


GPIOC_IEN

GPIO Port C Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_IEN GPIOC_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN0 IF_EN1 IF_EN2 IF_EN3 IF_EN4 IF_EN5 IF_EN8 IF_EN9 IF_EN10 IF_EN11 IF_EN12 IF_EN13 IR_EN0 IR_EN1 IR_EN2 IR_EN3 IR_EN4 IR_EN5 IR_EN8 IR_EN9 IR_EN10 IR_EN11 IR_EN12 IR_EN13

IF_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN12 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN13 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.


GPIOC_ISRC

GPIO Port C Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOC_ISRC GPIOC_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC0 ISRC1 ISRC2 ISRC3 ISRC4 ISRC5 ISRC8 ISRC9 ISRC10 ISRC11 ISRC12 ISRC13

ISRC0 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC4 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC5 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC8 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC9 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC10 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC11 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC12 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC13 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.


GPIOA_DMASK

GPIO Port A Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOA_DMASK GPIOA_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK10 DMASK11 DMASK12 DMASK13 DMASK14 DMASK15

DMASK10 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK11 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK12 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK13 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK14 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK15 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.


GPIOD_PMD

GPIO Port D Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_PMD GPIOD_PMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD8 PMD9 PMD10 PMD11

PMD0 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD1 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD2 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD3 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD4 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD5 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD8 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD9 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD10 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

PMD11 : GPIOx I/O Pin[n] Mode Control\nDetermine each I/O type of GPIOx pins.\nNote:\nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


GPIOD_OFFD

GPIO Port D Pin OFF Digital Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_OFFD GPIOD_OFFD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFD0 OFFD1 OFFD2 OFFD3 OFFD4 OFFD5 OFFD8 OFFD9 OFFD10 OFFD11

OFFD0 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD1 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD2 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD3 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD4 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD5 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD8 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD9 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD10 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.

OFFD11 : GPIOx Pin[n] OFF Digital Input Path Enable\nEach of these bits is used to control if the input path of corresponding GPIO pin is disabled. If input is analog signal, user can OFF digital input path to avoid creepage\nNotes: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

IO digital input path Enabled

#1 : 1

IO digital input path Disabled (digital input tied to low)

End of enumeration elements list.


GPIOD_DOUT

GPIO Port D Data Output Value
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DOUT GPIOD_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT8 DOUT9 DOUT10 DOUT11

DOUT0 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT1 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT2 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT3 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT4 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT5 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT8 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT9 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT10 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.

DOUT11 : GPIOx Pin[n] Output Value\nEach of these bits control the status of a GPIO pin when the GPIO pin is configures as output, open-drain and quasi-mode.\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIO port [A/B/C/D/ F] Pin[n] will drive Low if the GPIO pin is configures as output, open-drain and quasi-mode

#1 : 1

GPIO port [A/B/C/DF] Pin[n] will drive High if the GPIO pin is configures as output, open-drain and quasi-mode

End of enumeration elements list.


GPIOD_DMASK

GPIO Port D Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DMASK GPIOD_DMASK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMASK0 DMASK1 DMASK2 DMASK3 DMASK4 DMASK5 DMASK8 DMASK9 DMASK10 DMASK11

DMASK0 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK1 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK2 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK3 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK4 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK5 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK8 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK9 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK10 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.

DMASK11 : Port [A/B/C/D/ F] Data Output Write Mask\nThese bits are used to protect the corresponding register of GPIOx_DOUT bit[n]. When set the DMASK bit[n] to 1, the corresponding GPIOx_DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored\nNote: This function only protect corresponding GPIOx_DOUT[n] bit, and will not protect corresponding bit control register (GPIOAx_DOUT, GPIOBx_DOUT, GPIOCx_DOUT, GPIODx_DOUT and GPIOFx_DOUT).\nNote: \nGPIOA: valid n are 15~10. Others are reserved.\nGPIOB: valid n are 15~12, 10~0. Others are reserved.\nGPIOC: valid n are 13~8, 5~0. Others are reserved.\nGPIOD: valid n are 11~8, 5~0. Others are reserved.\nGPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The corresponding GPIOx_DOUT[n] bit can be updated

#1 : 1

The corresponding GPIOx_DOUT[n] bit is protected

End of enumeration elements list.


GPIOD_PIN

GPIO Port D Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

GPIOD_PIN GPIOD_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN8 PIN9 PIN10 PIN11

PIN0 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-only

PIN8 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port [A/B/C/D/ F] Pin Values Each bit of the register reflects the actual status of the respective GPIO pin If bit is 1, it indicates the corresponding pin status is high, else the pin status is low Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-only


GPIOD_DBEN

GPIO Port D De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_DBEN GPIOD_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN0 DBEN1 DBEN2 DBEN3 DBEN4 DBEN5 DBEN8 DBEN9 DBEN10 DBEN11

DBEN0 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN1 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN2 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN3 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN4 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN5 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN8 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN9 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN10 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.

DBEN11 : Port [A/B/C/D/ F] Input Signal De-bounce Enable DBEN[n]used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBNCECON[4], one de-bounce sample cycle is controlled by DBNCECON[3:0] The DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: GPIOA: valid n are 15~10. Others are reserved. GPIOB: valid n are 15~12, 10~0. Others are reserved. GPIOC: valid n are 13~8, 5~0. Others are reserved. GPIOD: valid n are 11~8, 5~0. Others are reserved. GPIOF: valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit[n] de-bounce function is disabled

#1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


GPIOD_IMD

GPIO Port D Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IMD GPIOD_IMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMD0 IMD1 IMD2 IMD3 IMD4 IMD5 IMD8 IMD9 IMD10 IMD11

IMD0 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD1 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD2 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD3 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD4 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD5 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD8 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD9 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD10 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.

IMD11 : Port [A/B/C/D/ F] Edge or Level Detection Interrupt Control\nIMD[n] is used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nIf pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge trigger interrupt

#1 : 1

Level trigger interrupt

End of enumeration elements list.


GPIOD_IEN

GPIO Port D Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_IEN GPIOD_IEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IF_EN0 IF_EN1 IF_EN2 IF_EN3 IF_EN4 IF_EN5 IF_EN8 IF_EN9 IF_EN10 IF_EN11 IR_EN0 IR_EN1 IR_EN2 IR_EN3 IR_EN4 IR_EN5 IR_EN8 IR_EN9 IR_EN10 IR_EN11

IF_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IF_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Falling Edge or Input Level Low IF_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When set the IF_EN[n] bit to 1: If the interrupt is level triggered, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from high-to-low will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] state low-level or high-to-low change interrupt Disabled

#1 : 1

PIN[n] state low-level or high-to-low change interrupt Enabled

End of enumeration elements list.

IR_EN0 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN1 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN2 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN3 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN4 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN5 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN8 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN9 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN10 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.

IR_EN11 : Port [A/B/C/D/ F] Interrupt Enable by Input Rising Edge or Input Level High IR_EN[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit to 1 also enable the pin wake-up function When the IR_EN[n] bit is set to 1: If the interrupt is level triggered, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge triggered, the input PIN[n] state changes from low-to-high will generate the interrupt. Note: GPIOA: Valid n are 15~10. Others are reserved. GPIOB: Valid n are 15~12, 10~0. Others are reserved. GPIOC: Valid n are 13~8, 5~0. Others are reserved. GPIOD: Valid n are 11~8, 5~0. Others are reserved. GPIOF: Valid n are 3~0. Others are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

PIN[n] level-high or low-to-high interrupt Disabled

#1 : 1

PIN[n] level-high or low-to-high interrupt Enabled

End of enumeration elements list.


GPIOD_ISRC

GPIO Port D Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIOD_ISRC GPIOD_ISRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISRC0 ISRC1 ISRC2 ISRC3 ISRC4 ISRC5 ISRC8 ISRC9 ISRC10 ISRC11

ISRC0 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC1 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC2 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC3 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC4 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC5 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC8 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC9 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC10 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.

ISRC11 : Port [A/B/C/D/ F] Interrupt Trigger Source Indicator\nRead:\nNote: \nGPIOA: Valid n are 15~10. Others are reserved.\nGPIOB: Valid n are 15~12, 10~0. Others are reserved.\nGPIOC: Valid n are 13~8, 5~0. Others are reserved.\nGPIOD: Valid n are 11~8, 5~0. Others are reserved.\nGPIOF: Valid n are 3~0. Others are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at GPIOx[n].\nNo action

#1 : 1

Indicates GPIOx[n] generate an interrupt.\nClear the corresponding pending interrupt

End of enumeration elements list.



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