I2CON

I2CLK

I2CTOC

I2CADDR1

I2CADDR2

I2CADDR3

I2CADM0

I2CADM1

I2CADM2

I2CADM3

I2CWKUPCON

I2CADDR0

I2CWKUPSTS

I2CDAT

I2CSTATUS

AA : Assert Acknowledge Control Bit\n
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI is by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control Bit In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a Slave mode, setting STO resets I2C hardware to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control Bit\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

ENS1 : I2C Controller Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EI : Enable Interrupt\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CLK : I2C clock divided Register\n
bits : 0 - 7 (8 bit)
access : read-write

TIF : Time-Out Flag\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV4 : Time-out Counter Input Clock Divided by 4\nWhen Enabled, the time-out period is extend 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENTI : Time-out Counter Enable/Disable\nWhen Enabled, the 14-bit time-out counter will start counting when SI is cleared. Setting the flag SI to high will reset counter and re-start counting up after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CADM : I2C Address Mask Register\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, it means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKUPEN : I2C Wake-up Function Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2CADDR : I2C Address Register\nThe content of this register is irrelevant when I2C is in Master mode. In Slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the addresses is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKUPIF : Wake-up Interrupt Flag\nSoftware can write one to clear this flag
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

I2CDAT : I2C Data Register\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

I2CSTATUS : I2C Status Register\nThe status register of I2C:\n
bits : 0 - 7 (8 bit)
access : read-only