TCSR0

TCAP0

TEXCON0

TEXISR0

TCSR1

TCMPR1

TISR1

TDR1

TCAP1

TEXCON1

TEXISR1

TCMPR0

TISR0

TDR0

PRESCALE : Pre-scale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable\nWhen TDR_EN is set, TDR (Timer Data Register) will be updated continuously with the 24-bit up-timer value as the timer is counting.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : Wake-up Enable\nWhen WAKE_EN is set and the TIF is set, the timer controller will generator a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTB : Counter Mode Enable Bit \nThis bit is the counter mode enable bit. When Timer is used as an event counter, this bit should be set to 1 and Timer will work as an event counter. The counter detect phase can be selected as rising/falling edge of external pin by TX_PHASE field.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACT : Timer Active Status Bit (Read only)\nThis bit indicates the up-timer status.\n
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRST : Timer Reset Bit\nSet this bit will reset the 24-bit up-timer, 8-bit pre-scale counter and also force CEN to 0.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write

IE : Interrupt Enable Bit\nIf timer interrupt is enabled, the timer asserts its interrupt signal when the associated up-timer value is equal to TCMPR.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CEN : Timer Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_TMR : ICE debug mode acknowledge Disable (Write-protection Bit)\nTIMER counter will keep going no matter ICE debug mode acknowledged or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP : Timer Capture Data Register\nWhen TEXEN (TEXCON[3]) is set, RSTCAPn(TTXCON[4]) is 0, and the transition on the TEX pins associated TEX_EDGE(TEXCON[2:1]) setting is occurred, the internal 24-bit up-timer value will be loaded into TCAP. User can read this register for the counter value.
bits : 0 - 23 (24 bit)
access : read-only

TX_PHASE : Timer External Count Phase \nThis bit indicates the external count pin phase.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEX_EDGE : Timer External Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXEN : Timer External Pin Enable \nThis bit enables the reset/capture function on the TEX pin. \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCAPn : Timer External Reset Counter/Capture Mode Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIEN : Timer External Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXDB : Timer External Capture Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of T0EX~T3EX pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCDB : Timer Counter Pin De-bounce Enable Bit\nIf this bit is enabled, the edge of TM0~TM3 pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIF : Timer External Interrupt Flag\nThis bit indicates the external interrupt status of Timer.\nThis bit is set by hardware when TEXEN (TEXCON[3]) is to 1, and the transition on the TEX pins associated with TEX_EDGE (TEXCON[2:1]) setting is occurred. It is cleared by writing 1 to this bit.\n
bits : 0 - 0 (1 bit)
access : read-write

TCMP : Timer Compared Value\nNote1: Never write 0x0 or 0x1 in TCMP, or the core will run into unknown state.\nNote2: When timer is operating in continuous counting mode, the 24-bit up-timer will count continuously if software writes a new value into TCMP. If timer is operating at other modes, the 24-bit up-timer will restart counting and using newest TCMP value to be the compared value if software writes a new value into TCMP.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt status of timer.\nTIF bit is set by hardware when the up counting value of internal 24-bit up-timer matches the timer compared value (TCMP). It is cleared by writing 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write

TWF : Timer Wakeup Flag\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high.\nIt must be cleared by software with a write 1 to this bit.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR : Timer Data Register User can read TDR for getting current 24- bits up event counter value if TCSR[24] is 1
bits : 0 - 23 (24 bit)
access : read-only