\n

WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR

WTCRALT


WTCR

Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR WTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTR WTRE WTRF WTIF WTWKE WTWKF WTIE WTE WTIS DBGACK_WDT

WTR : Clear Watchdog Timer (Write-protection Bit)\nSetting this bit will clear the Watchdog timer.\nNote: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset the contents of the Watchdog timer

End of enumeration elements list.

WTRE : Watchdog Timer Reset Enable (Write-protection Bit)\nSetting this bit will enable the Watchdog timer reset function.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset function Disabled

#1 : 1

Watchdog timer reset function Enabled

End of enumeration elements list.

WTRF : Watchdog Timer Reset Flag\nWhen the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, the Watchdog timer has no effect on this bit.\nNote: This bit is cleared by writing 1 to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset did not occur

#1 : 1

Watchdog timer reset occurred

End of enumeration elements list.

WTIF : Watchdog Timer Interrupt Flag\nIf the Watchdog timer interrupt is enabled, the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred.\nNote: This bit is cleared by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer interrupt did not occur

#1 : 1

Watchdog timer interrupt occurred

End of enumeration elements list.

WTWKE : Watchdog Timer Wake-up Function Enable bit (Write-protection Bit)\nNote: Chip can be woken up by WDT only if WDT clock source select RC10K.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer Wake-up chip function Disabled

#1 : 1

Wake-up function Enabled so that Watchdog timer time-out can wake-up chip from Power-down mode

End of enumeration elements list.

WTWKF : Watchdog Timer Wake-up Flag\nIf Watchdog timer causes chip to wake up from Power-down mode, this bit will be set to high. It must be cleared by software by writing 1 to this bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer does not cause chip wake up

#1 : 1

Chip woken up from Idle or Power-down mode by Watchdog time-out

End of enumeration elements list.

WTIE : Watchdog Timer Interrupt Enable (Write-protection Bit)\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer interrupt Disabled

#1 : 1

Watchdog timer interrupt Enabled

End of enumeration elements list.

WTE : Watchdog Timer Enable (Write-protection Bit)\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer Disabled (This action will reset the internal counter)

#1 : 1

Watchdog timer Enabled

End of enumeration elements list.

WTIS : Watchdog Timer Interval Selection (Write-protection Bit)\n
bits : 8 - 10 (3 bit)
access : read-write

DBGACK_WDT : ICE Debug Mode Acknowledge Disable (Write-protection Bit)\nWatchdog Timer counter will keep going no matter ICE debug mode acknowledged or not.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement affects Watchdog Timer counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


WTCRALT

Watchdog Timer Alternative Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCRALT WTCRALT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTRDSEL

WTRDSEL : Watchdog Timer Reset Delay Select (Write-protection Bits) When watchdog time-out happened, software has a time named watchdog reset delay period to clear watchdog timer to prevent watchdog reset happened. Software can select a suitable value of watchdog reset delay period for different watchdog time-out period. These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Reference the register REGWRPROT at address GCR_BA+0x100. This register will be reset if watchdog reset happened
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Watchdog reset delay period is 1024 watchdog clock

#01 : 1

Watchdog reset delay period is 128 watchdog clock

#10 : 2

Watchdog reset delay period is 16 watchdog clock

#11 : 3

Watchdog reset delay period is 1 watchdog clock

End of enumeration elements list.



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