WWDTRLD

WWDTCR

WWDTSTS

WWDTCVR

WWDTRLD : WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value larger than WINCMP, WWDT will generate RESET signal.
bits : 0 - 31 (32 bit)
access : write-only

WWDTEN : WWDT Enable\nSet this bit to enable the Window Watchdog timer.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDTIE : WWDT Interrupt Enable\nSet this bit to enable the Watchdog timer interrupt function.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIODSEL : WWDT Pre-scale Period Select\n
bits : 8 - 11 (4 bit)
access : read-write

WINCMP : WWDT Window Compare Register\nSet this register to adjust the valid reload window. \nNote: Software can only write WWDTRLD when WWDT counter value between 0 and WINCMP. If software writes WWDTRLD when WWDT counter value is larger than WWCMP, WWDT will generate RESET signal.
bits : 16 - 21 (6 bit)
access : read-write

DBGACK_WWDT : ICE debug mode acknowledge Disable\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDTIF : WWDT Compare Match Interrupt Flag\nWhen WWCMP matches the WWDT counter, this bit is set to 1. This bit will be cleared by software write 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write

WWDTRF : WWDT Reset Flag\nWhen WWDT counter counts down to 0 or writes WWDTRLD during WWDT counter larger than WINCMP, chip will be reset and this bit is set to 1. Software can write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

WWDTCVAL : WWDT Counter Value\nThis register reflects the counter value of window watchdog. This register is read only.
bits : 0 - 5 (6 bit)
access : read-only