PS2CON

PS2TXDATA3

PS2RXDATA

PS2STATUS

PS2INTID

PS2TXDATA0

PS2TXDATA1

PS2TXDATA2

PS2EN : Enable PS/2 Device\nEnable PS/2 device controller.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINTEN : Enable Transmit Interrupt\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINTEN : Enable Receive Interrupt\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFIFODIPTH : Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACK : Acknowledge Enable\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRFIFO : Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY bit in PS2STATUS bit will be set to 1 and pointer BYTEIDEX is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVERRIDE : Software Override PS/2 CLK/DATA Pin State\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPS2CLK : Force PS2CLK Line\nIt forces PS2CLK line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPS2DAT : Force PS2DATA Line\nIt forces PS2DATA high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PS2RXDATA : Received Data For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register. CPU must read this register before next byte reception complete otherwise, the data will be overwritten and RXOVF bit in PS2STATUS[6] will be set to 1.
bits : 0 - 7 (8 bit)
access : read-only

PS2CLK : CLK Pin State\nThis bit reflects the status of the PS2CLK line after synchronizing.
bits : 0 - 0 (1 bit)
access : read-write

PS2DATA : DATA Pin State\nThis bit reflects the status of the PS2DATA line after synchronizing and sampling.
bits : 1 - 1 (1 bit)
access : read-write

FRAMERR : Frame Error For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides PS2CLK to send clock till PS2DATA release to high state. After that, device sends a Resend command to host. Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPARITY : Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nRead only bit.
bits : 3 - 3 (1 bit)
access : read-write

RXBUSY : Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nRead only bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXBUSY : Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nRead only bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVF : RX Buffer Overwrite\nWrite 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : TX FIFO Empty\nWhen software writes any data to PS2TXDATA0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nRead only bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYTEIDX : Byte Index\n
bits : 8 - 11 (4 bit)
access : read-write

RXINT : Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINT : Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXINTEN bit is set to 1.\nWrite 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PS2TXDATAx : Transmit data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write