I2S_CON (CON)

I2S_TXFIFO (TXFIFO)

I2S_RXFIFO (RXFIFO)

I2S_CLKDIV (CLKDIV)

I2S_IE (IE)

I2S_STATUS (STATUS)

I2SEN : I2S Controller Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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TXEN : Transmit enable\n
bits : 1 - 1 (1 bit)
access : read-write

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RXEN : Receive enable\n
bits : 2 - 2 (1 bit)
access : read-write

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MUTE : Transmit Mute Enable\n
bits : 3 - 3 (1 bit)
access : read-write

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WORDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write

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MONO : Monaural Data\n
bits : 6 - 6 (1 bit)
access : read-write

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FORMAT : Data format Selection\n
bits : 7 - 7 (1 bit)
access : read-write

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SLAVE : Slave mode\nI2S can be operated as Master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC123 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXTH : Transmit FIFO threshold level\nIf remain data word (32 bits) in transmit FIFO is the same or less than threshold level, the TXTHF flag is set.\n
bits : 9 - 11 (3 bit)
access : read-write

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RXTH : Receive FIFO threshold level\nWhen received data word(s) in buffer is equal to or higher than threshold level, the RXTHF flag is set.\n
bits : 12 - 14 (3 bit)
access : read-write

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MCLKEN : Master clock enable\nFor NuMicro( NUC123 series, if the external crystal clock is frequency 2*N*256fs, software can program MCLK_DIV[2:0] in I2S_CLKDIV register to get 256fs clock to audio codec chip.\n
bits : 15 - 15 (1 bit)
access : read-write

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RCHZCEN : Right Channel Zero-cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n
bits : 16 - 16 (1 bit)
access : read-write

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LCHZCEN : Left Channel Zero Cross Detect Enable\nIf this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1.\n
bits : 17 - 17 (1 bit)
access : read-write

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CLR_TXFIFO : Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXFIFO_LEVEL[3:0] returns to zero and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically, reading it returns zero.
bits : 18 - 18 (1 bit)
access : read-write

CLR_RXFIFO : Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXFIFO_LEVEL[3:0] returns to zero and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically, reading it returns zero.
bits : 19 - 19 (1 bit)
access : read-write

TXDMA : Enable Transmit DMA\nWhen TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
bits : 20 - 20 (1 bit)
access : read-write

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RXDMA : Enable Receive DMA\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
bits : 21 - 21 (1 bit)
access : read-write

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RXLCH : Receive Left Channel Enable\n
bits : 23 - 23 (1 bit)
access : read-write

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PCM : PCM Interface Enable\n
bits : 24 - 24 (1 bit)
access : read-write

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End of enumeration elements list.

TXFIFO : Transmit FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data transmission. Write data to this register to prepare data for transmit. The remaining word number is indicated by TX_LEVEL[3:0] in I2S_STATUS.
bits : 0 - 31 (32 bit)
access : read-write

RXFIFO : Receive FIFO register\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in I2S_STATUS register.
bits : 0 - 31 (32 bit)
access : read-write

MCLK_DIV : Master Clock Divider\nIf chip external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLK_DIV is set to 0, MCLK is the same as external clock input.\n
bits : 0 - 2 (3 bit)
access : read-write

BCLK_DIV : Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by NuMicro( NUC123 series. Software can program these bits to generate sampling rate clock frequency.\n
bits : 8 - 15 (8 bit)
access : read-write

RXUDFIE : Receive FIFO Underflow Interrupt Enable\nIf software reads the received FIFO when it is empty, RXUDF flag in I2SSTATUS register is set to 1.\n
bits : 0 - 0 (1 bit)
access : read-write

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RXOVFIE : Receive FIFO Overflow Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

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RXTHIE : Received FIFO Threshold Level Interrupt Enable\nWhen data word in receive FIFO is equal to or higher then RXTH[2:0] and the RXTHF bit is set to 1. If RXTHIE bit is enabled, interrupt occurs.\n
bits : 2 - 2 (1 bit)
access : read-write

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TXUDFIE : Transmitted FIFO Underflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO underflow flag is set to 1.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXOVFIE : Transmitted FIFO Overflow Interrupt Enable\nInterrupt occurs if this bit is set to 1 and transmitted FIFO overflow flag is set to 1.\n
bits : 9 - 9 (1 bit)
access : read-write

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TXTHIE : Transmitted FIFO Threshold Level Interrupt Enable\nInterrupt occurs if this bit is set to 1 and data words in transmit FIFO are less than TXTH[2:0].\n
bits : 10 - 10 (1 bit)
access : read-write

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RZCIE : Right Channel Zero-cross Interrupt Enable\n
bits : 11 - 11 (1 bit)
access : read-write

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LZCIE : Left Channel Zero-cross Interrupt Enable\nInterrupt occurs if this bit is set to 1 and left channel zero-cross.\n
bits : 12 - 12 (1 bit)
access : read-write

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I2SINT : I2S Interrupt Flag\nIt is wire-OR of I2STXINT and I2SRXINT bits.\nThis bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

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I2SRXINT : I2S Receive Interrupt\nThis bit is read only.
bits : 1 - 1 (1 bit)
access : read-write

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I2STXINT : I2S Transmit Interrupt\nThis bit is read only.
bits : 2 - 2 (1 bit)
access : read-write

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RIGHT : Right Channel\nThis bit indicates the current transmit data is belong to right channel.\nThis bit is read only.
bits : 3 - 3 (1 bit)
access : read-write

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RXUDF : Receive FIFO Underflow Flag\nRead receive FIFO when it is empty, this bit set to 1 indicate underflow occur.\nSoftware can write 1 to clear this bit to zero.
bits : 8 - 8 (1 bit)
access : read-write

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RXOVF : Receive FIFO Overflow Flag\nWhen receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nSoftware can write 1 to clear this bit to zero.
bits : 9 - 9 (1 bit)
access : read-write

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RXTHF : Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal or higher than threshold value set in RXTH[2:0] the RXTHF bit becomes to 1. It keeps at 1 till RXFIFO_LEVEL[3:0] less than RXTH[1:0] after software read RXFIFO register.\nThis bit is read only.
bits : 10 - 10 (1 bit)
access : read-write

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RXFULL : Receive FIFO Full\nThis bit reflect data words number in receive FIFO is 8.\nThis bit is read only.
bits : 11 - 11 (1 bit)
access : read-write

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RXEMPTY : Receive FIFO Empty\nThis bit reflects data words number in receive FIFO is zero.\nThis bit is read only.
bits : 12 - 12 (1 bit)
access : read-write

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TXUDF : Transmit FIFO underflow flag\nWhen transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nSoftware can write 1 to clear this bit to zero
bits : 16 - 16 (1 bit)
access : read-write

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TXOVF : Transmit FIFO Overflow Flag\nWrite data to transmit FIFO when it is full and this bit set to 1.\nSoftware can write 1 to clear this bit to zero.
bits : 17 - 17 (1 bit)
access : read-write

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End of enumeration elements list.

TXTHF : Transmit FIFO Threshold Flag\nWhen data word(s) in transmit FIFO is equal to or lower than threshold value set in TXTH[2:0] the TXTHF bit becomes to 1. It keeps at 1 till TXFIFO_LEVEL[3:0] is higher than TXTH[1:0] after software write TXFIFO register.\nThis bit is read only.
bits : 18 - 18 (1 bit)
access : read-write

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TXFULL : Transmit FIFO Full\nThis bit reflect data word number in transmit FIFO is 8.\nThis bit is read only
bits : 19 - 19 (1 bit)
access : read-write

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TXEMPTY : Transmit FIFO Empty\nThis bit reflect data word number in transmit FIFO is zero.\nThis bit is read only.
bits : 20 - 20 (1 bit)
access : read-write

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TXBUSY : Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out, and set to 1 when the 1st data is load to shift buffer. \nThis bit is read only.
bits : 21 - 21 (1 bit)
access : read-write

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RZCF : Right Channel Zero-cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero.
bits : 22 - 22 (1 bit)
access : read-write

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LZCF : Left Channel Zero-cross Flag\nIt indicates left channel next the sample data sign bit is changed or all data bits are zero.\nSoftware can write 1 to clear this bit to zero
bits : 23 - 23 (1 bit)
access : read-write

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RX_LEVEL : Receive FIFO Level\nThese bits indicate word number in receive FIFO.\n
bits : 24 - 27 (4 bit)
access : read-write

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TX_LEVEL : Transmit FIFO Level\nThese bits indicate word number in transmit FIFO.\n
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.