UA_RBR

UA_THR

UA_FSR

UA_ISR

UA_TOR

UA_BAUD

UA_IRCR

UA_ALT_CSR

UA_FUN_SEL

UA_IER

UA_FCR

UA_LCR

RBR : Receive Buffer Register (Read Only)\nBy reading this register, the UART will return the 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the TX pin.
bits : 0 - 7 (8 bit)
access : write-only

RX_OVER_IF : RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow. \nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, 16 bytes of UART0/UART1/UART2, this bit will be set.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDIF : Auto-Baud Rate Detect Interrupt (Read Only) \nThis bit is set to logic "1" when auto-baud rate detect function is finished. \nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDTOIF : Auto-Baud Rate Time-Out Interrupt (Read Only) \nNote1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.\nNote2: This bit is read only, but can be cleared by writing "1" to it.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RS485_ADD_DETF : RS-485 Address Byte Detection Flag (Read Only) (Available In UART0/UART1)\nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PEF : Parity Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FEF : Framing Error Flag (Read Only)\nThis bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0), and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BIF : Break Interrupt Flag (Read Only)\nThis bit is set to logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_POINTER : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, then RX_POINTER increases one. When one byte of RX FIFO is read by CPU, then RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15 (UART0/UART1/UART2). When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15 (UART0/UART1/UART2).\nWhen RX Buffer is equal to 1, if one byte data is received, the RX_FULL bit is set to 1 and RX_POINTER will show 1. Once the RX Buffer is read, the RX_POINTER is 0.
bits : 8 - 13 (6 bit)
access : read-only

RX_EMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of RX Buffer has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_FULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO is full or not (UART0/UART1/UART2). \nNote: This bit is set when the number of usage in RX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_POINTER : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, then TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, then TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15 (UART0/UART1/UART2). When the using level of TX FIFO Buffer is equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15 (UART0/UART1/UART2).\nTX_POINTER is 0 (UART3/URT4/UART5).\nWhen TX Buffer is equal to 1, if one byte data is received, the TX_FULL bit is set to 1 and TX_POINTER will show 1. Once the TX Buffer is read, the TX_POINTER is 0.
bits : 16 - 21 (6 bit)
access : read-only

TX_EMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not. (UART0/UART1/UART2)\nNote: When the last byte of TX Buffer has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_FULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not. (UART0/UART1/UART2)\nThis bit is set when the number of usage in TX Buffer is equal to 1 (UART3/UART4/UART5), otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_OVER_IF : TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1. (UART0/UART1/UART2)\nNote: This bit is read only, but can be cleared by writing "1" to it.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TE_FLAG : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. (UART0/UART1/UART2)\nNote: This bit is cleared automatically when TX FIFO/TX Buffer is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDA_IF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) equals the RFITL then the RDA_IF(UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UA_FCR[7:4]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_IF : Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]), FEF(UA_FSR[5]) and PEF(UA_FSR[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_IF : MODEM Interrupt Flag (Read Only) (Not Available In UART2 Channel)\nNote: This bit is read only and reset to 0 when bit DCTSF is cleared by a write 1 on DCTSF(UA_MSR[0]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_IF : Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO (UART0/UART1/UART2) / RX Buffer (UART3/UART4/UART5) is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOUT_IEN (UA_IER [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UA_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_IF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO (UART0/UART1/UART2) / TX Buffer (UART3/UART4/UART5) or RX FIFO (UART0/UART1/UART2)/ RX Buffer (UART3/UART4/UART5) overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set). When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [8]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is read only and reset to 0 when all bits of TX_OVER_IF(UA_FSR[24]) and RX_OVER_IF(UA_FSR[0]) are cleared.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WKIF : UART Wake-Up Flag (Read Only)\nThis bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.\nNote: This bit is read only. This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_IF : LIN Bus Flag (Read Only)(UART0/UARt1/UART2)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[9]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDA_INT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_INT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1])and THRE_IF(UA_SR[1]) are both set to 1.\n
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_INT : Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2]) and RLS_IF(UA_ISR[2]) are both set to 1.\n
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_INT : MODEM Status Interrupt Indicator (Read Only) (Available In UART0/UART1 Channel)\nThis bit is set if MODEM_IEN(UA_IER[3] and MODEM_IF(UA_ISR[4]) are both set to 1\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_INT : Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN(UA_IER[4]) and TOUT_IF(UA_ISR[4]) are both set to 1.\n
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_INT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN(UA_IER[5] and BUF_ERR_IF(UA_ISR[5]) are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_INT : LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF(UA_ISR[7]) are both set to 1.\n
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSWKIF : NCTS Wake-Up Interrupt Flag (Read Only)\nNote1: If WKCTSIEN (UA_IER[6])is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATWKIF : Data Wake-Up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATIEN (UA_IER[10]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-Out Interrupt Comparator\n
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider\nThe field indicates the baud rate divider.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER_X : Divider X\n
bits : 24 - 27 (4 bit)
access : read-write

DIV_X_ONE : Divider X Equal To 1\nRefer to Table 624 UART Baud Rate Equation for more information.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV_X_EN : Divider X Enable Control\nRefer to Table 624 UART Baud Rate Equation for more information.\nNote: In IrDA mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : IrDA Receiver/Transmitter Selection Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : IrDA Inverse Transmitting Output Signal Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : IrDA Inverse Receive Input Signal Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_BKFL : UART LIN Break Field Length (Available In UART0/UART1/UART2)\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is LIN_BKFL + 1.\n
bits : 0 - 3 (4 bit)
access : read-write

LIN_RX_EN : LIN RX Enable Control (Available In UART0/UART1/UART2)\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Break Mode Enable Control (Available In UART0/UART1/UART2)\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_NMM : RS-485 Normal Multi-Drop Operation Mode (NMM) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AAD : RS-485 Auto Address Detection Operation Mode (AAD) (Available In UART0/UART1)\nNote: It cannot be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AUD : RS-485 Auto Direction Mode (AUD) (Available In UART0/UART1)\nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_ADD_EN : RS-485 Address Detection Enable Control (Available In UART0/UART1)\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRIF : Auto-Baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_IEN [18]) is set then the auto-baud rate interrupt will be generated. \nNote: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UA_FSR[2]) and ABRDIF(UA_FSR[1]).
bits : 17 - 17 (1 bit)
access : read-only

ABRDEN : Auto-Baud Rate Detect Enable Control\nThis bit is cleared automatically after auto-baud detection is finished.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDBITS : Auto-Baud Rate Detect Bit Length \nNote: The calculation of bit number includes the START bit.
bits : 19 - 20 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_MATCH : Address Match Value Register (Available In UART0/UART1)\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable Control\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IEN : Receive Data Available Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IEN : Transmit Holding Register Empty Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IEN : Receive Line Status Interrupt Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IEN : Modem Status Interrupt Enable Control (Available In UART0/UART1 Channel)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUT_IEN : RX Time-Out Interrupt Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IEN : Buffer Error Interrupt Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKCTSIEN : NCTS Wake-Up Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_IEN : LIN Bus Interrupt Enable Control\nNote: This field is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKDATIEN : Incoming Data Wake-Up Interrupt Enable Control\nNote: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIME_OUT_EN : Time-Out Counter Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTS Auto Flow Control Enable Control ( Available In UART0/UART1 Channel)\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR [19:16]), the UART will de-assert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTS Auto Flow Control Enable Control (Available In UART0/UART1 Channel)\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRIEN : Auto-Baud Rate Interrupt Enable Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFR : RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO /receive buffer and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFR : TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO/ transmit buffer and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripherial clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt (INT_RDA) Trigger Level (Available In UART0/UART1/UART2 Channel)\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if UA_IER [RDA_IEN] enabled, and an interrupt will be generated).\n
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_DIS : Receiver Disable Control\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UA_ALT_CSR[8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_TRI_LEV : RTS Trigger Level For Auto-Flow Control Use (Available In UART0/UART1 Channel)\nNote: This field is used for RTS auto-flow control.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number Of "STOP Bit"\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Control\nThis bit has effect only when PBE (UA_LCR[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write