ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPSTA

ISPDAT

ISPCMD

ISPEN : ISP Enable Bit (Write Protect )\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect )\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in CONFIG0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Enable Config Update By ISP (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0\n(2) LDROM writes to itself if LDUEN is set to 0\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear to this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger (Write-Protection Bit)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates Data Flash start address. It is read only.\nFor 128 KB flash memory device, the Data Flash size is defined by user configuration, register content is loaded from CONFIG1 when chip is powered on but for 64/32 KB device, it is fixed at 0x0001_F000.
bits : 0 - 31 (32 bit)
access : read-only

FOMSEL0 : Chip Frequency Optimization Mode Select 0 (Write-Protection Bit)\nWhen CPU frequency is lower than 72 MHz, user can modify flash access delay cycle by FOMSEL1 and FOMSEL0 to improve system performance.\n
bits : 4 - 4 (1 bit)
access : read-write

FOMSEL1 : Chip Frequency Optimization Mode Select1 (Write-protection Bit)
bits : 6 - 6 (1 bit)
access : read-write

ISPADR : ISP Address\nThe NuMicro( NUC230/240 series has a maximum of 32Kx32 (128 KB) embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPGO : ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same as ISPTRG bit0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Chip Boot Selection (Read Only)\nThis is a mirror of CBS in CONFIG0.
bits : 1 - 2 (2 bit)
access : read-only

ISPFF : ISP Fail Flag (Write-Protection Bit)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself\n(2) LDROM writes to itself\n(3) CONFIG is erased/programmed if CFGUEN is set to 0\n(4) Destination address is illegal, such as over an available range\nWrite 1 to clear this bit.\nNote: The function of this bit is the same as ISPCON bit6
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
bits : 9 - 20 (12 bit)
access : read-only

ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

ISPCMD : ISP Command\nISP command table is shown below:\n
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.