I2SCON

I2STXFIFO

I2SRXFIFO

I2SCLKDIV

I2SIE

I2SSTATUS

I2SEN : I2S Controller Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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TXEN : Transmit Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

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RXEN : Receive Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

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MUTE : Transmit Mute Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

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WORDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write

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MONO : Monaural Data\n
bits : 6 - 6 (1 bit)
access : read-write

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FORMAT : Data Format\n
bits : 7 - 7 (1 bit)
access : read-write

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SLAVE : Slave Mode\nI2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC230/240 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXTH : Transmit FIFO Threshold Level\nIf the count of remaining data word (32 bits) in transmit FIFO is equal to or less than threshold level then TXTHF (I2SSTATUS[18]) is set.\n
bits : 9 - 11 (3 bit)
access : read-write

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RXTH : Receive FIFO Threshold Level\nWhen the count of received data word(s) in buffer is equal to or higher than threshold level, RXTHF (I2SSTATUS[10]) will be set.\n
bits : 12 - 14 (3 bit)
access : read-write

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MCLKEN : Master Clock Enable Bit\nIf MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.\n
bits : 15 - 15 (1 bit)
access : read-write

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RCHZCEN : Right Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
bits : 16 - 16 (1 bit)
access : read-write

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LCHZCEN : Left Channel Zero Cross Detection Enable Bit\nIf this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1. This function is only available in transmit operation.\n
bits : 17 - 17 (1 bit)
access : read-write

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CLR_TXFIFO : Clear Transmit FIFO\nWrite 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TX_LEVEL[3:0] returns to 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nThis bit is cleared by hardware automatically. Returns 0 on read.
bits : 18 - 18 (1 bit)
access : read-write

CLR_RXFIFO : Clear Receive FIFO\nWrite 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns 0 and receive FIFO becomes empty.\nThis bit is cleared by hardware automatically. Returns 0 on read.
bits : 19 - 19 (1 bit)
access : read-write

TXDMA : Transmit DMA Enable Bit\nWhen TX DMA is enabled, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.\n
bits : 20 - 20 (1 bit)
access : read-write

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RXDMA : Receive DMA Enable Bit\nWhen RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.\n
bits : 21 - 21 (1 bit)
access : read-write

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RXLCH : Receive Left Channel Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write

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TXFIFO : Transmit FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data transmit. Write data to this register to prepare data for transmission. The remaining word number is indicated by TX_LEVEL (I2SSTATUS[31:28])
bits : 0 - 31 (32 bit)
access : write-only

RXFIFO : Receive FIFO Register\nI2S contains 8 words (8x32 bits) data buffer for data receive. Read this register to get data of receive FIFO. The remaining data word number is indicated by RX_LEVEL (I2SSTATUS[27:24]).
bits : 0 - 31 (32 bit)
access : read-only

MCLK_DIV : Master Clock Divider\nIf MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. The master clock rate, F_MCLK, is determined by the following expressions.\nF_I2SCLK is the frequency of I2S peripheral clock.\nIn general, the master clock rate is 256 times sampling clock rate.
bits : 0 - 2 (3 bit)
access : read-write

BCLK_DIV : Bit Clock Divider\nThe I2S controller will generate bit clock in Master mode. The bit clock rate, F_BCLK, is determined by the following expression.\n
bits : 8 - 15 (8 bit)
access : read-write

RXUDFIE : Receive FIFO Underflow Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

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RXOVFIE : Receive FIFO Overflow Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

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RXTHIE : Receive FIFO Threshold Level Interrupt Enable Bit\nWhen the count of data words in receive FIFO is equal to or higher than RXTH (I2SCON[14:12]) and this bit is set to 1, receive FIFO threshold level interrupt will be asserted.\n
bits : 2 - 2 (1 bit)
access : read-write

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TXUDFIE : Transmit FIFO Underflow Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.\n
bits : 8 - 8 (1 bit)
access : read-write

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TXOVFIE : Transmit FIFO Overflow Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1\n
bits : 9 - 9 (1 bit)
access : read-write

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TXTHIE : Transmit FIFO Threshold Level Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and the count of data words in transmit FIFO is less than TXTH (I2SCON[11:9]).\n
bits : 10 - 10 (1 bit)
access : read-write

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RZCIE : Right Channel Zero-Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and right channel zero-cross event is detected.\n
bits : 11 - 11 (1 bit)
access : read-write

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LZCIE : Left Channel Zero-Cross Interrupt Enable Bit\nInterrupt occurs if this bit is set to 1 and left channel zero-cross event is detected.\n
bits : 12 - 12 (1 bit)
access : read-write

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I2SINT : I2S Interrupt Flag\nThis bit is wire-OR of I2STXINT and I2SRXINT bits.\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

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I2SRXINT : I2S Receive Interrupt\nNote: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-write

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I2STXINT : I2S Transmit Interrupt\nNote: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-write

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RIGHT : Right Channel\nThis bit indicates current transmit data is belong to which channel\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-write

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RXUDF : Receive FIFO Underflow Flag\nUnderflow event will occur if read the empty receive FIFO.\nNote: Write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

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RXOVF : Receive FIFO Overflow Flag\nWhen receive FIFO is full and hardware attempt to write data to receive FIFO, this bit will be set to 1, data in 1st buffer will be overwrote.\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

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RXTHF : Receive FIFO Threshold Flag\nWhen data word(s) in receive FIFO is equal to or larger than threshold value set in RXTH (I2SCON[14:12]). The RXTHF bit becomes to 1. It keeps at 1 till RX_LEVEL (I2SSTATUS[27:24]) is less than RXTH.\nNote: This bit is read only.
bits : 10 - 10 (1 bit)
access : read-write

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RXFULL : Receive FIFO Full\nThis bit reflects the count of data in receive FIFO is 8\nNote: This bit is read only.
bits : 11 - 11 (1 bit)
access : read-write

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RXEMPTY : Receive FIFO Empty\nThis bit reflects the count of data in receive FIFO is 0\nNote: This bit is read only.
bits : 12 - 12 (1 bit)
access : read-write

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TXUDF : Transmit FIFO Underflow Flag\nIf transmit FIFO is empty and hardware reads data from transmit FIFO. This bit will be set to 1.\nNote: Software can write 1 to clear this bit to 0.
bits : 16 - 16 (1 bit)
access : read-write

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TXOVF : Transmit FIFO Overflow Flag\nThis bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.\nNote: Write 1 to clear this bit to 0.
bits : 17 - 17 (1 bit)
access : read-write

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TXTHF : Transmit FIFO Threshold Flag\nWhen the count of data stored in transmit-FIFO is equal to or less than threshold value set in TXTH (I2SCON[11:9]). The TXTHF bit becomes to 1. It keeps at 1 till TX_LEVEL (I2SSTATUS[31:28]) is larger than TXTH.\nNote: This bit is read only.
bits : 18 - 18 (1 bit)
access : read-write

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TXFULL : Transmit FIFO Full\nThis bit reflects data word number in transmit FIFO is 8\nNote: This bit is read only.
bits : 19 - 19 (1 bit)
access : read-write

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TXEMPTY : Transmit FIFO Empty\nThis bit reflects data word number in transmit FIFO is 0\nNote: This bit is read only.
bits : 20 - 20 (1 bit)
access : read-write

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TXBUSY : Transmit Busy\nThis bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.\nNote: This bit is read only.
bits : 21 - 21 (1 bit)
access : read-write

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RZCF : Right Channel Zero-Cross Flag\nIt indicates the sign bit of right channel sample data is changed or all data bits are 0.\nNote: Write 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write

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LZCF : Left Channel Zero-Cross Flag\nIt indicates the sign bit of left channel sample data is changed or all data bits are 0.\nNote: Write 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

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RX_LEVEL : Receive FIFO Level\nThese bits indicate word number in receive FIFO\n
bits : 24 - 27 (4 bit)
access : read-write

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TX_LEVEL : Transmit FIFO Level\nThese bits indicate word number in transmit FIFO\n
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.