Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x160 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Init : Init Initialization\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Initialization is started
End of enumeration elements list.
IE : Module Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SIE : Status Change Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled - No Status Change Interrupt will be generated
#1 : 1
Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected
End of enumeration elements list.
EIE : Error Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled - No Error Status Interrupt will be generated
#1 : 1
Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt
End of enumeration elements list.
DAR : Automatic Re-Transmission Disable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic Retransmission of disturbed messages enabled
#1 : 1
Automatic Retransmission disabled
End of enumeration elements list.
CCE : Configuration Change Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No write access to the Bit Timing Register
#1 : 1
Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1)
End of enumeration elements list.
Test : Test Mode Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Test Mode
End of enumeration elements list.
Interrupt Identifier Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntId : Interrupt Identifier (Indicates The Source Of The Interrupt)\nIf several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the application software has cleared it. If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.\nThe Status Interrupt has the highest priority. Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.\nA message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). The Status Interrupt is cleared by reading the Status Register.
bits : 0 - 15 (16 bit)
access : read-only
Transmission Request Register 1
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TxRqst16_1 : Transmission Request Bits 16-1 (Of All Message Objects)\nThese bits are read only.
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This Message Object is not waiting for transmission
1 : 1
The transmission of this Message Object is requested and is not yet done
End of enumeration elements list.
Transmission Request Register 2
address_offset : 0x104 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TxRqst32_17 : Transmission Request Bits 32-17 (Of All Message Objects)\nThese bits are read only.
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This Message Object is not waiting for transmission
1 : 1
The transmission of this Message Object is requested and is not yet done
End of enumeration elements list.
New Data Register 1
address_offset : 0x120 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NewData16_1 : New Data Bits 16-1 (Of All Message Objects)\n
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
1 : 1
The Message Handler or the application software has written new data into the data portion of this Message Object
End of enumeration elements list.
New Data Register 2
address_offset : 0x124 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NewData32_17 : New Data Bits 32-17 (Of All Message Objects)\n
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software
1 : 1
The Message Handler or the application software has written new data into the data portion of this Message Object
End of enumeration elements list.
Test Register (Register Map Note 1)
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Res : Reserved\nThere are reserved bits.\nThese bits are always read as '0' and must always be written with '0'.
bits : 0 - 1 (2 bit)
access : read-write
Basic : Basic Mode\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Basic Mode disabled
#1 : 1
IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer
End of enumeration elements list.
Silent : Silent Mode\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
The module is in Silent Mode
End of enumeration elements list.
LBack : Loop Back Mode Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Loop Back Mode is disabled
#1 : 1
Loop Back Mode is enabled
End of enumeration elements list.
Tx : Tx[1:0]: Control Of CAN_TX Pin\n
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reset value, CAN_TX pin is controlled by the CAN Core
#01 : 1
Sample Point can be monitored at CAN_TX pin
#10 : 2
CAN_TX pin drives a dominant ('0') value
#11 : 3
CAN_TX pin drives a recessive ('1') value
End of enumeration elements list.
Rx : Monitors The Actual Value Of CAN_RX Pin (Read Only) \n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN bus is dominant (CAN_RX = '0')
#1 : 1
The CAN bus is recessive (CAN_RX = '1')
End of enumeration elements list.
Interrupt Pending Register 1
address_offset : 0x140 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntPnd16_1 : Interrupt Pending Bits 16-1 (Of All Message Objects)\n
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This message object is not the source of an interrupt
1 : 1
This message object is the source of an interrupt
End of enumeration elements list.
Interrupt Pending Register 2
address_offset : 0x144 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IntPnd32_17 : Interrupt Pending Bits 32-17(Of All Message Objects)\n
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This message object is not the source of an interrupt
1 : 1
This message object is the source of an interrupt
End of enumeration elements list.
Message Valid Register 1
address_offset : 0x160 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MsgVal16_1 : Message Valid Bits 16-1 (Of All Message Objects) (Read Only)\nEx. CAN_MVLD1[0] means Message object No.1 is valid or not. If CAN_MVLD1[0] is set, message object No.1 is configured.
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This Message Object is ignored by the Message Handler
1 : 1
This Message Object is configured and should be considered by the Message Handler
End of enumeration elements list.
Message Valid Register 2
address_offset : 0x164 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MsgVal32_17 : Message Valid Bits 32-17 (Of All Message Objects) (Read Only)\nEx.CAN_MVLD2[15] means Message object No.32 is valid or not. If CAN_MVLD2[15] is set, message object No.32 is configured.
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : 0
This Message Object is ignored by the Message Handler
1 : 1
This Message Object is configured and should be considered by the Message Handler
End of enumeration elements list.
Wake-up Enable Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKUP_EN : Wake-Up Enable Bit\nNote: User can wake-up system when there is a falling edge in the CAN_Rx pin..
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The wake-up function Disabled
#1 : 1
The wake-up function Enabled
End of enumeration elements list.
Wake-up Status Register
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKUP_STS : Wake-Up Status \nNote: This bit can be cleared by writing '0'.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wake-up event occurred
#1 : 1
Wake-up event occurred
End of enumeration elements list.
Baud Rate Prescaler Extension Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRPE : BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
bits : 0 - 3 (4 bit)
access : read-write
IFn (Register Map Note 2) Command Request Registers
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MessageNumber : Message Number\n0x01-0x20: Valid Message Number, the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number, interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
bits : 0 - 5 (6 bit)
access : read-write
Busy : Busy Flag\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read/write action has finished
#1 : 1
Writing to the IFn Command Request Register is in progress. This bit can only be read by the software
End of enumeration elements list.
IFn Command Mask Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT_B : Access Data Bytes [7:4]\nWrite Operation: \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Bytes [7:4] unchanged
#1 : 1
Transfer Data Bytes [7:4] to Message Object.\nTransfer Data Bytes [7:4] to IFn Message Buffer Register
End of enumeration elements list.
DAT_A : Access Data Bytes [3:0]\nWrite Operation:\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data Bytes [3:0] unchanged
#1 : 1
Transfer Data Bytes [3:0] to Message Object.\nTransfer Data Bytes [3:0] to IFn Message Buffer Register
End of enumeration elements list.
TxRqst_NewDat : Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
TxRqst bit unchanged.\nNewDat bit remains unchanged
#1 : 1
Set TxRqst bit.\nClear NewDat bit in the Message Object
End of enumeration elements list.
ClrIntPnd : Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object, this bit is ignored.\nRead Operation:\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
IntPnd bit (CAN_IFn_MCON[13]) remains unchanged
#1 : 1
Clear IntPnd bit in the Message Object
End of enumeration elements list.
Control : Control Access Control Bits\nWrite Operation:\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control Bits unchanged
#1 : 1
Transfer Control Bits to Message Object.\nTransfer Control Bits to IFn Message Buffer Register
End of enumeration elements list.
Arb : Access Arbitration Bits\nWrite Operation:\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Arbitration bits unchanged
#1 : 1
Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_ARB2[15]) to Message Object.\nTransfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register
End of enumeration elements list.
Mask : Access Mask Bits\nWrite Operation:\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask bits unchanged
#1 : 1
Transfer Identifier Mask + MDir + MXtd to Message Object.\nTransfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register
End of enumeration elements list.
WR_RD : Write / Read Mode\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers
#1 : 1
Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register
End of enumeration elements list.
IFn Mask 1 Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Msk : Identifier Mask 15-0\n
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
1 : 1
The corresponding identifier bit is used for acceptance filtering
End of enumeration elements list.
IFn Mask 2 Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Msk : Identifier Mask 28-16\n
bits : 0 - 12 (13 bit)
access : read-write
Enumeration:
0 : 0
The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering
1 : 1
The corresponding identifier bit is used for acceptance filtering
End of enumeration elements list.
MDir : Mask Message Direction\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering
#1 : 1
The message direction bit (Dir) is used for acceptance filtering
End of enumeration elements list.
MXtd : Mask Extended Identifier\nNote: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The extended identifier bit (IDE) has no effect on the acceptance filtering
#1 : 1
The extended identifier bit (IDE) is used for acceptance filtering
End of enumeration elements list.
IFn Arbitration 1 Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Message Identifier 15-0\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
bits : 0 - 15 (16 bit)
access : read-write
IFn Arbitration 2 Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Message Identifier 28-16\nID28 - ID0, 29-bit Identifier ("Extended Frame").\nID28 - ID18, 11-bit Identifier ("Standard Frame")
bits : 0 - 12 (13 bit)
access : read-write
Dir : Message Direction\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Direction is receive
#1 : 1
Direction is transmit
End of enumeration elements list.
Xtd : Extended Identifier\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The 11-bit ("standard") Identifier will be used for this Message Object
#1 : 1
The 29-bit ("extended") Identifier will be used for this Message Object
End of enumeration elements list.
MsgVal : Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_ARB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Message Object is ignored by the Message Handler
#1 : 1
The Message Object is configured and should be considered by the Message Handler
End of enumeration elements list.
IFn Message Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DLC : Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.\nData 0: 1st data byte of a CAN Data Frame\nData 1: 2nd data byte of a CAN Data Frame\nData 2: 3rd data byte of a CAN Data Frame\nData 3: 4th data byte of a CAN Data Frame\nData 4: 5th data byte of a CAN Data Frame\nData 5: 6th data byte of a CAN Data Frame\nData 6: 7th data byte of a CAN Data Frame\nData 7 : 8th data byte of a CAN Data Frame\nNote: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. I f the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
bits : 0 - 3 (4 bit)
access : read-write
EoB : End Of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer
#1 : 1
Single Message Object or last Message Object of a FIFO Buffer
End of enumeration elements list.
TxRqst : Transmit Request\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
This Message Object is not waiting for transmission
#1 : 1
The transmission of this Message Object is requested and is not yet done
End of enumeration elements list.
RmtEn : Remote Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged
#1 : 1
At the reception of a Remote Frame, TxRqst is set
End of enumeration elements list.
RxIE : Receive Interrupt Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame
#1 : 1
IntPnd will be set after a successful reception of a frame
End of enumeration elements list.
TxIE : Transmit Interrupt Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame
#1 : 1
IntPnd will be set after a successful transmission of a frame
End of enumeration elements list.
UMask : Use Acceptance Mask\nNote: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask ignored
#1 : 1
Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
End of enumeration elements list.
IntPnd : Interrupt Pending\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
This message object is not the source of an interrupt
#1 : 1
This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority
End of enumeration elements list.
MsgLst : None
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No message lost since last time this bit was reset by the CPU
#1 : 1
The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message
End of enumeration elements list.
NewDat : New Data\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software
#1 : 1
The Message Handler or the application software has written new data into the data portion of this Message Object
End of enumeration elements list.
IFn Data A1 Register (Register Map Note 3)
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data0 : Data Byte 0\n1st data byte of a CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
Data1 : Data Byte 1\n2nd data byte of a CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEC : Last Error Code (Type Of The Last Error To Occur On The CAN Bus)\nThe LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. The unused code '7' may be written by the CPU to check for updates. The following table describes the error code.
bits : 0 - 2 (3 bit)
access : read-write
TxOK : Transmitted A Message Successfully\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Since this bit was reset by the CPU, no message has been successfully transmitted. This bit is never reset by the CAN Core
#1 : 1
Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted
End of enumeration elements list.
RxOK : Received A Message Successfully\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No message has been successfully received since this bit was last reset by the CPU. This bit is never reset by the CAN Core
#1 : 1
A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering)
End of enumeration elements list.
EPass : Error Passive (Read Only)\n
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN Core is error active
#1 : 1
The CAN Core is in the error passive state as defined in the CAN Specification
End of enumeration elements list.
EWarn : Error Warning Status (Read Only)\n
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
Both error counters are below the error warning limit of 96
#1 : 1
At least one of the error counters in the EML has reached the error warning limit of 96
End of enumeration elements list.
BOff : Bus-Off Status (Read Only) \n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
The CAN module is not in bus-off state
#1 : 1
The CAN module is in bus-off state
End of enumeration elements list.
IFn Data A2 Register (Register Map Note 3)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data2 : Data Byte 2\n3rd data byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
Data3 : Data Byte 3\n4th data byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
IFn Data B1 Register (Register Map Note 3)
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data4 : Data Byte 4\n5th data byte of CAN Data Frame
bits : 0 - 7 (8 bit)
access : read-write
Data5 : Data Byte 5\n6th data byte of CAN Data Frame
bits : 8 - 15 (8 bit)
access : read-write
IFn Data B2 Register (Register Map Note 3)
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data6 : Data Byte 6\n7th data byte of CAN Data Frame.
bits : 0 - 7 (8 bit)
access : read-write
Data7 : Data Byte 7\n8th data byte of CAN Data Frame.
bits : 8 - 15 (8 bit)
access : read-write
Error Counter Register
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TEC : Transmit Error Counter\nActual state of the Transmit Error Counter. Values between 0 and 255.
bits : 0 - 7 (8 bit)
access : read-only
REC : Receive Error Counter\nActual state of the Receive Error Counter. Values between 0 and 127.
bits : 8 - 14 (7 bit)
access : read-only
RP : Receive Error Passive\n
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The Receive Error Counter is below the error passive level
#1 : 1
The Receive Error Counter has reached the error passive level as defined in the CAN Specification
End of enumeration elements list.
IFn (Register Map Note 2) Command Request Registers
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Command Mask Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Mask 1 Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Mask 2 Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Arbitration 1 Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Arbitration 2 Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Message Control Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Data A1 Register (Register Map Note 3)
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Data A2 Register (Register Map Note 3)
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Data B1 Register (Register Map Note 3)
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFn Data B2 Register (Register Map Note 3)
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Bit Timing Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRP : Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. The bit time is built up from a multiple of this quanta. Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
bits : 0 - 5 (6 bit)
access : read-write
SJW : (Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0 ... 3]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
bits : 6 - 7 (2 bit)
access : read-write
TSeg1 : Time Segment Before The Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1 ... 15]. The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
bits : 8 - 11 (4 bit)
access : read-write
TSeg2 : Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0 ... 7]. The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
bits : 12 - 14 (3 bit)
access : read-write
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