\n
address_offset : 0x0 Bytes (0x0)
size : 0x88 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 (BOD) Interrupt Source Identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ4 (GPA/GPB) Interrupt Source Identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: GPB_INT\nBit0: GPA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ5 (GPC/GPD/GPE/GPF) Interrupt Source Identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: GPF_INT\nBit2: GPE_INT\nBit1: GPD_INT\nBit0: GPC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ6 (PWMA) Interrupt Source Identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM3_INT\nBit2: PWM2_INT\nBit1: PWM1_INT\nBit0: PWM0_INT
bits : 0 - 3 (4 bit)
access : read-only
IRQ7 (PWMB) Interrupt Source Identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit3: PWM7_INT\nBit2: PWM6_INT\nBit1: PWM5_INT\nBit0: PWM4_INT
bits : 0 - 3 (4 bit)
access : read-only
IRQ8 (TMR0) Interrupt Source Identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0 \nBit0: TMR0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ9 (TMR1) Interrupt Source Identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: TMR1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ10 (TMR2) Interrupt Source Identity
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: TMR2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ11 (TMR3) Interrupt Source Identity
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: TMR3_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ12 (UART0/UART2) Interrupt Source Identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 \nBit1: UART2_INT\nBit0: UART0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ13 (UART1) Interrupt Source Identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: UART1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ14 (SPI0) Interrupt Source Identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ15 (SPI1) Interrupt Source Identity
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: SPI1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ1 (WDT) Interrupt Source Identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: WWDT_INT\nBit0: WDT_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ16 (SPI2) Interrupt Source Identity
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: SPI2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ17 (SPI3) Interrupt Source Identity
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: SPI3_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ18 (I2C0) Interrupt Source Identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 \nBit1: 0\nBit0: I2C0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ19 (I2C1) Interrupt Source Identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0 \nBit1: 0\nBit0: I2C1_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Reserved
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ22 (SC0/SC1/SC2) Interrupt Source Identity
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: SC2_INT \nBit1: SC1_INT\nBit0: SC0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ23 (USB) Interrupt Source Identity
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: USB_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ24 (PS/2) Interrupt Source Identity
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: PS2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ25 (ACMP) Interrupt Source Identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: ACMP_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ26 (PDMA) Interrupt Source Identity
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: PDMA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ27 (I2S) Interrupt Source Identity
address_offset : 0x6C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: I2S_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ28 (PWRWU) Interrupt Source Identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: PWRWU_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ29 (ADC) Interrupt Source Identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: ADC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ30 (IRCT) Interrupt Source Identity
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: IRCT_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ31 (RTC) Interrupt Source Identity
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: RTC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ2 (EINT0) Interrupt Source Identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: EINT0 - external interrupt 0
bits : 0 - 2 (3 bit)
access : read-only
NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of the peripheral interrupt by setting NMI_SEL.
bits : 0 - 4 (5 bit)
access : read-write
NMI_EN : NMI Interrupt Enable Bit (Write Protect)
Note: This bit is the protected bit, and programming it needs to write 59h , 16h , and 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
NMI interrupt Disabled
#1 : 1
NMI interrupt Enabled
End of enumeration elements list.
MCU Interrupt Request Source Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0. There are two modes to generate interrupt to Cortex-M0, the normal mode and test mode.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0: Set MCU_IRQ[n] 1 will generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1 (mean an interrupt is assert), setting 1 to the MCU_IRQ[n] 1 will clear the interrupt and setting MCU_IRQ[n] 0: has no effect
bits : 0 - 31 (32 bit)
access : read-write
IRQ3 (EINT1) Interrupt Source Identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Bit2: 0\nBit1: 0\nBit0: EINT1 - external interrupt 1
bits : 0 - 2 (3 bit)
access : read-only
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.