\n
address_offset : 0xD00 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
CPUID Register
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Read as 0x0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Read as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only
PART : Read as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only
IMPLEMENTER : None
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Contains the Active Exception Number\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
VECTPENDING : Indicates the Exception Number of the Highest Priority Pending Enabled Exception:\n
bits : 12 - 17 (6 bit)
access : read-write
Enumeration:
0 : 0
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag, Excluding NMI and Faults:\nThis bit is read only.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt not pending
#1 : 1
Interrupt pending
End of enumeration elements list.
ISRPREEMPT : If Set, a Pending Exception Will Be Serviced on Exit From the Debug Halt State\nThis bit is read only.
bits : 23 - 23 (1 bit)
access : read-write
PENDSTCLR : SysTick Exception Clear-pending Bit
Write:
This is a write only bit. When you want to clear PENDST bit, you must write 0 to PENDSTSET and write 1 to PENDSTCLR at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending Bit\nWrite:\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nSysTick exception is not pending
#1 : 1
Changes SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV Clear-pending Bit
Write:
This is a write only bit. When you want to clear PENDSV bit, you must write 0 to PENDSVSET and write 1 to PENDSVCLR at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV Set-pending Bit\nWrite:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPendSV exception is not pending
#1 : 1
Changes PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI Set-pending Bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNMI exception not pending
#1 : 1
Changes NMI exception state to pending.\nNMI exception pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Setting this Bit to 1 Will Clear All Active State Information for Fixed and Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : Writing this Bit 1 Will Cause a Reset Signal to Be Asserted to the Chip to Indicate a Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
VECTORKEY : When writing this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates Sleep-on-exit When Returning From Handler Mode to Thread Mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not sleep when returning to Thread mode
#1 : 1
Enter sleep, or deep sleep, on return from an ISR to Thread mode
End of enumeration elements list.
SLEEPDEEP : Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode:\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sleep
#1 : 1
Deep sleep
End of enumeration elements list.
SEVONPEND : Send Event on Pending Bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only enabled interrupts or events can wake-up the processor, disabled interrupts are excluded
#1 : 1
Enabled events and all interrupts, including disabled interrupts, can wake-up the processor
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority
bits : 30 - 31 (2 bit)
access : read-write
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