\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALE : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write
TDR_EN : Data Load Enable\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Data Register update Disabled
#1 : 1
Timer Data Register update Enabled while timer counter is active
End of enumeration elements list.
WAKE_EN : Wake-up Enable\nIf this bit is set to 1, while timer interrupt flag (TISR[0] TIF) is generated to 1 and IE (TCSR[29] interrupt enable bit) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up trigger event Disabled if timer interrupt signal generated
#1 : 1
Wake-up trigger event Enabled if timer interrupt signal generated
End of enumeration elements list.
CTB : Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source. Please refer to 6.7.4.5 for detail description.\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
External counter mode Disabled
#1 : 1
External counter mode Enabled
End of enumeration elements list.
CACT : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
CRST : Timer Reset Bit\nSetting this bit will reset the 24-bit up counter value (TDR) and also force CEN (TCSR[30] timer enable bit) to 0 if CACT (TCSR[25] timer active status bit) is 1.\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset 8-bit prescale counter, 24-bit up counter value and CEN bit
End of enumeration elements list.
MODE : Timer Operating Mode\n
bits : 27 - 28 (2 bit)
access : read-write
IE : Interrupt Enable Bit\nIf this bit is enabled, when the timer interrupt flag (TISR[0] TIF) is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Interrupt Disabled
#1 : 1
Timer Interrupt Enabled
End of enumeration elements list.
CEN : Timer Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
DBGACK_TMR : ICE Debug Mode Acknowledge Disable (Write Protected)\nTIMER counter will keep going no matter CPU is held by ICE or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
Timer0 Capture Data Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TCAP : Timer Capture Data Register
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, TEXIF (TEXISR[0] timer external interrupt flag) will set to 1 and the current timer counter value (TDR value) will be auto-loaded into this TCAP field.
bits : 0 - 23 (24 bit)
access : read-only
Timer0 External Control Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PHASE : Timer External Count Phase \nThis bit indicates the detection phase of external counting pin.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A falling edge of external counting pin will be counted
#1 : 1
A rising edge of external counting pin will be counted
End of enumeration elements list.
TEX_EDGE : Timer External Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
A 1 to 0 transition on TMx_EXT pin will be detected
#01 : 1
A 0 to 1 transition on TMx_EXT pin will be detected
#10 : 2
Either 1 to 0 or 0 to 1 transition on TMx_EXT pin will be detected
#11 : 3
Reserved
End of enumeration elements list.
TEXEN : Timer External Pin Enable \nThis bit enables the RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select ) function on the TMx_EXT pin. \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
RSTCAPSEL function of TMx_EXT pin will be ignored
#1 : 1
RSTCAPSEL function of TMx_EXT pin is active
End of enumeration elements list.
RSTCAPSEL : Timer External Reset Counter / Capture Mode Select\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transition on TMx_EXT pin is using to save the 24-bit timer counter value (TDR value) to timer capture value (TCAP value) if TEXIF (TEXISR[0] timer external interrupt flag) is set to 1
#1 : 1
Transition on TMx_EXT pin is using to reset the 24-bit timer counter
End of enumeration elements list.
TEXIEN : Timer External Interrupt Enable\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT pin detection Interrupt Disabled
#1 : 1
TMx_EXT pin detection Interrupt Enabled
End of enumeration elements list.
TEXDB : Timer External Capture Pin De-bounce Enable \nIf this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx_EXT pin de-bounce Disabled
#1 : 1
TMx_EXT pin de-bounce Enabled
End of enumeration elements list.
TCDB : Timer Counter Pin De-bounce Enable\nIf this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TMx pin de-bounce Disabled
#1 : 1
TMx pin de-bounce Enabled
End of enumeration elements list.
Timer0 External Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEXIF : Timer External Interrupt Flag
This bit indicates the timer external interrupt flag status.
When TEXEN (TEXCON[3] timer external pin enable) bit is set, RSTCAPSEL (TEXCON[4] timer external reset counter/capture mode select) bit is 0, and a transition on TMx_EXT pin matched the TEX_EDGE (TEXCON[2:1] timer external pin edge detect) setting, this bit will set to 1 by hardware.
This bit is cleared by writing 1 to it through software.
bits : 0 - 0 (1 bit)
access : read-write
Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 Capture Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer1 External Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] timet interrupt flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest TCMP value to be the timer compared value if software writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write
Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer.\nAnd this bit is set by hardware when the timer counter value) matches the timer compared value (TCMP value). It is cleared by writing 1 to it through software.
bits : 0 - 0 (1 bit)
access : read-write
TWF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nIt must be cleared by writing 1 to it through software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Idle or power-down mode if timer interrupt signal generated
End of enumeration elements list.
Timer0 Data Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDR : Timer Data Register\nIf TDR_EN (TCSR[16]) is set to 1, TDR will be updated continuously to monitor 24-bit timer counter value.
bits : 0 - 23 (24 bit)
access : read-only
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