\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x18 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number\nThis register reflects device part number code. S/W can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Peripheral Controller Reset Control Register 3
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SC0RST : SC0 Controller Reset\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC0 controller normal operation
#1 : 1
SC0 controller reset
End of enumeration elements list.
SC1RST : SC1 Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC1 controller normal operation
#1 : 1
SC1 controller reset
End of enumeration elements list.
SC2RST : SC2 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC2 controller normal operation
#1 : 1
SC2 controller reset
End of enumeration elements list.
SC3RST : SC3 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC3 controller normal operation
#1 : 1
SC3 controller reset
End of enumeration elements list.
SC4RST : SC4 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC4 controller normal operation
#1 : 1
SC4 controller reset
End of enumeration elements list.
SC5RST : SC5 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SC5 controller normal operation
#1 : 1
SC5 controller reset
End of enumeration elements list.
I2C4RST : I2C4 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C4 controller normal operation
#1 : 1
I2C4 controller reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 controller normal operation
#1 : 1
PWM0 controller reset
End of enumeration elements list.
PWM1RST : PWM1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 controller normal operation
#1 : 1
PWM1 controller reset
End of enumeration elements list.
QEI0RST : QEI0 Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI0 controller normal operation
#1 : 1
QEI0 controller reset
End of enumeration elements list.
QEI1RST : QEI1 Controller Reset\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
QEI1 controller normal operation
#1 : 1
QEI1 controller reset
End of enumeration elements list.
Register Write-protection Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Write-Protection Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Write-Protection Disable Index (Read Only)
The Protected registers are:
SYS_IPRST0: address 0x4000_0008
SYS_BODCTL: address 0x4000_0018
SYS_PORCTL: address 0x4000_0024
PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select)
NMI_SEL]: address 0x4000_0300 (for NMI source select)
ISPCON: address 0x4000_5000 (Flash ISP Control register)
ISPTRG: address 0x4000_5010 (ISP Trigger Control register)
WTCR: address 0x4004_0000
FATCON: address 0x4000_5018
TAMPER: address 0x400E_1000
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-Out Detector Enable Bit (Write Protect)
The default value is set by flash controller user configuration register config0 bit[23]
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled
#1 : 1
Brown-out Detector function Enabled
End of enumeration elements list.
BODVL : Brown-Out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register config0 bit[22:21]
Relationship between BODVL and Brown-out voltage listed below:
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
2.2V
#01 : 1
2.7V
#10 : 2
3.7V
#11 : 3
4.5V
End of enumeration elements list.
BODRSTEN : Brown-Out Reset Enable Bit (Write Protect)
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high. BOD interrupt will keep till to the BODEN set to 0. BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
The default value is set by flash controller user configuration register config0 bit[20].
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out INTERRUPT function Enabled
#1 : 1
Brown-out RESET function Enabled
End of enumeration elements list.
BODINTF : Brown-Out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting
#1 : 1
When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODLPM : Brown-Out Detector Low Power Mode (Write Protect)
The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD operate in normal mode (default)
#1 : 1
BOD Low Power mode Enabled
End of enumeration elements list.
BODOUT : Brown-Out Detector Output Status\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0. It means the detected voltage is higher than BODVL setting or BODEN is 0
#1 : 1
Brown-out Detector output status is 1. It means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0000
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)
The LVR function reset the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default)
End of enumeration elements list.
Temperature Sensor Control Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nAfter this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function chapter for details.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
Hardware Version Control Register
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VCID : Hardware Version Control (Ready Only)
These registers repress hardware version.
These bits are the read protected bits.
It means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-only
Power-On-reset Controller Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-On-Reset Enable Bit (Write Protect)
When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 0 - 15 (16 bit)
access : read-write
ADC VREF Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREFCTL : VREF Control Bits (Write Protect)\n
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
#00011 : 3
VREF is internal 2.65V
#00111 : 7
VREF is internal 2.048V
#01011 : 11
VREF is internal 3.072V
#01111 : 15
VREF is internal 4.096V
#10000 : 16
VREF is from AVDD
End of enumeration elements list.
ADCMODESEL : ADC IP Selection (Write Protect)\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC mode
#1 : 1
E ADC mode
End of enumeration elements list.
PWMSYNCMODE : PWM SYNC MODE (Write Protect)\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM SYNC MODE Disabled PWM engine clock can different with HCLK
#1 : 1
PWM SYNC MODE Enabled PWM engine clock is same as HCLK
End of enumeration elements list.
USB PHY Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBROLE : USB Role Configuration (Write Protect)\nUSB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard USB device
#01 : 1
Standard USB host
#10 : 2
ID dependent device
#11 : 3
On-The-Go device
End of enumeration elements list.
LDO33EN : LDO33 Enable Bit (Write Protect) \n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB LDO33 Disabled
#1 : 1
USB LDO33 Enabled
End of enumeration elements list.
Port A Low Byte Multi-function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port A High Byte Multi-function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port B Low Byte Multi-function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port B High Byte Multi-function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : nRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
Note1: Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer or window watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
SYSRF : System Reset Flag
The system reset flag is set by the Reset Signal from the Cortex-M4 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M4
#1 : 1
The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M4 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
Port C Low Byte Multi-function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port C High Byte Multi-function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port D Low Byte Multi-function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD5MFP : PD.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port D High Byte Multi-function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD8MFP : PD.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PD9MFP : PD.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PD10MFP : PD.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PD11MFP : PD.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PD12MFP : PD.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PD13MFP : PD.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port E Low Byte Multi-function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE0MFP : PE.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE1MFP : PE.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE2MFP : PE.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE3MFP : PE.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE4MFP : PE.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE6MFP : PE.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE7MFP : PE.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port E High Byte Multi-function Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE8MFP : PE.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PE9MFP : PE.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PE10MFP : PE.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PE11MFP : PE.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PE12MFP : PE.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PE13MFP : PE.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PE14MFP : PE.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PE15MFP : PE.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port F Low Byte Multi-function Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF4MFP : PF.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF5MFP : PF.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port F High Byte Multi-function Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF8MFP : PF.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PF9MFP : PF.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PF10MFP : PF.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PF11MFP : PF.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PF12MFP : PF.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PF13MFP : PF.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PF14MFP : PF.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PF15MFP : PF.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port G Low Byte Multi-function Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG0MFP : PG.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PG1MFP : PG.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PG2MFP : PG.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PG3MFP : PG.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PG4MFP : PG.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PG5MFP : PG.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PG6MFP : PG.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PG7MFP : PG.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port G High Byte Multi-function Control Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PG8MFP : PG.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PG9MFP : PG.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PG10MFP : PG.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PG11MFP : PG.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PG12MFP : PG.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PG13MFP : PG.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PG14MFP : PG.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PG15MFP : PG.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port H Low Byte Multi-function Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH0MFP : PH.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PH1MFP : PH.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PH2MFP : PH.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PH3MFP : PH.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PH4MFP : PH.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PH5MFP : PH.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PH6MFP : PH.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PH7MFP : PH.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port H High Byte Multi-function Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PH8MFP : PH.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PH9MFP : PH.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PH10MFP : PH.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PH11MFP : PH.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PH12MFP : PH.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PH13MFP : PH.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PH14MFP : PH.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PH15MFP : PH.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port I Low Byte Multi-function Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI0MFP : PI.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PI1MFP : PI.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PI2MFP : PI.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PI3MFP : PI.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PI4MFP : PI.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PI5MFP : PI.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PI6MFP : PI.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PI7MFP : PI.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Port I High Byte Multi-function Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PI8MFP : PI.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
PI9MFP : PI.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
PI10MFP : PI.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
PI11MFP : PI.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
PI12MFP : PI.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
PI13MFP : PI.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
PI14MFP : PI.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
PI15MFP : PI.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Peripheral Controller Reset Control Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-Shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
This bit is a write protected bit, which means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one shot reset
End of enumeration elements list.
CPURST : Processor Core One-Shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA controller normal operation
#1 : 1
PDMA controller reset
End of enumeration elements list.
EBIRST : EBI Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the EBI. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI controller normal operation
#1 : 1
EBI controller reset
End of enumeration elements list.
USBHRST : USBH Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the HSB HOST controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
USBH controller normal operation
#1 : 1
USBH controller reset
End of enumeration elements list.
EMACRST : EMAC Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the EMAC controller. User needs to set this bit to 0 to release from the reset state.
This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC controller normal operation
#1 : 1
EMAC controller reset
End of enumeration elements list.
SDHRST : SD HOST Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the SD HOST controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD HOST controller normal operation
#1 : 1
SD HOST controller reset
End of enumeration elements list.
CRCRST : CRC Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRC controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Reference the register SYS_REGLCTL at address GCR_BA+0x100
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRC controller normal operation
#1 : 1
CRC controller reset
End of enumeration elements list.
CAPRST : Image Capture Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CAP controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Reference the register SYS_REGLCTL at address GCR_BA+0x100
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAP controller normal operation
#1 : 1
CAP controller reset
End of enumeration elements list.
CRPTRST : CRYPTO Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the CRYPTO controller. User needs to set this bit to 0 to release from the reset state.
This bit is a write protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRYPTO controller normal operation
#1 : 1
CRYPTO controller reset
End of enumeration elements list.
Peripheral Controller Reset Control Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO controller normal operation
#1 : 1
GPIO controller reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 controller normal operation
#1 : 1
Timer0 controller reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 controller normal operation
#1 : 1
Timer1 controller reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 controller normal operation
#1 : 1
Timer2 controller reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 controller normal operation
#1 : 1
Timer3 controller reset
End of enumeration elements list.
ACMPRST : Analog Comparator Controller Reset\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator controller normal operation
#1 : 1
Analog Comparator controller reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 controller normal operation
#1 : 1
I2C0 controller reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 controller normal operation
#1 : 1
I2C1 controller reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 controller normal operation
#1 : 1
SPI0 controller reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 controller normal operation
#1 : 1
SPI1 controller reset
End of enumeration elements list.
SPI2RST : SPI2 Controller Reset \n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2 controller normal operation
#1 : 1
SPI2 controller reset
End of enumeration elements list.
SPI3RST : SPI3 Controller Reset \n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI3 controller normal operation
#1 : 1
SPI3 controller reset
End of enumeration elements list.
UART0RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 controller normal operation
#1 : 1
UART0 controller reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 controller normal operation
#1 : 1
UART1 controller reset
End of enumeration elements list.
UART2RST : UART2 Controller Reset \n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART2 controller normal operation
#1 : 1
UART2 controller reset
End of enumeration elements list.
UART3RST : UART3 Controller Reset \n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART3 controller normal operation
#1 : 1
UART3 controller reset
End of enumeration elements list.
UART4RST : UART4 Controller Reset \n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART4 controller normal operation
#1 : 1
UART4 controller reset
End of enumeration elements list.
UART5RST : UART2 Controller Reset \n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART5 controller normal operation
#1 : 1
UART5 controller reset
End of enumeration elements list.
CAN0RST : CAN0 Controller Reset\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN0 controller normal operation
#1 : 1
CAN0 controller reset
End of enumeration elements list.
CAN1RST : CAN1 Controller Reset\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAN1 controller normal operation
#1 : 1
CAN1 controller reset
End of enumeration elements list.
USBDRST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB device controller normal operation
#1 : 1
USB device controller reset
End of enumeration elements list.
EADCRST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC controller normal operation
#1 : 1
ADC controller reset
End of enumeration elements list.
I2SRST : I2S Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S controller normal operation
#1 : 1
I2S controller reset
End of enumeration elements list.
I2S1RST : I2S1 Controller Reset\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S1 controller normal operation
#1 : 1
I2S1 controller reset
End of enumeration elements list.
PS2RST : PS/2 Controller Reset\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PS/2 controller normal operation
#1 : 1
PS/2 controller reset
End of enumeration elements list.
SRAM Failed Interrupt Enable Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRIEN : SRAM Parity Check Fail Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAMF INT Disabled
#1 : 1
SRAMF INT Enabled when SRAM fail flag
End of enumeration elements list.
SRAM Parity Check Error Flag
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERRIF0 : SRAM Parity Check Fail Flag\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No first 1 SRAM fail
#1 : 1
First SRAM Fail
End of enumeration elements list.
PERRIF1 : SRAM Parity Check Fail Flag\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
2nd SRAM fail
#1 : 1
2nd SRAM Fail
End of enumeration elements list.
SRAM Parity Check Error First Address1
address_offset : 0xC8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERRADDR : First SRAM Parity Check Fail Address\nThis register shows the first system SRAM parity error byte address.
bits : 0 - 31 (32 bit)
access : read-only
SRAM Parity Check Error First Address2
address_offset : 0xCC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PERRADDR : Second SRAM Parity Check Fail Address\nThis register shows the second system SRAM parity error byte address.
bits : 0 - 31 (32 bit)
access : read-only
IRC Trim Control Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of HIRC auto trim.\nIf no any target frequency is selected (FREQSEL is 00), the HIRC auto trim function is disabled.\nDuring auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC auto trim function
#01 : 1
Enable HIRC auto trim function and trim HIRC to 22.1184 MHz
#10 : 2
Enable HIRC auto trim function and trim HIRC to 24 MHz
#11 : 3
Reserved
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nFor example, if CALCLOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#01 : 1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#10 : 2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#11 : 3
Trim value calculation is based on average difference in 32 32.768 kHz clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64
#01 : 1
Trim retry count limitation is 128
#10 : 2
Trim retry count limitation is 256
#11 : 3
Trim retry count limitation is 512
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
IRC Trim Interrupt Enable Control Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.\nIf this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF status to trigger an interrupt to CPU
End of enumeration elements list.
IRC Trim Interrupt Status Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically if CESTOPEN is set to 1.\nIf this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
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