\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 ~ IRQ159 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ159 Set-enable Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-Pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ159 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-pending Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-pending Control Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-pending Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt Clear-Pending\nThe NVIC_ICPR0-NCVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ159 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-pending Control Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-pending Control Register
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-pending Control Register
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Active Bit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active. \n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ0 ~ IRQ159 Active Bit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Active Bit Register
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Active Bit Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Active Bit Register
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4n0 : Priority Of IRQ_4n+0
0 denotes the highest priority and 15 denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write
PRI_4n1 : Priority Of IRQ_4n+1
0 denotes the highest priority and 15 denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write
PRI_4n2 : Priority Of IRQ_4n+2
0 denotes the highest priority and 15 denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write
PRI_4n3 : Priority Of IRQ_4n+3
0 denotes the highest priority and 15 denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x35C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x364 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x368 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x36C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x370 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x374 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x378 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Interrupt Priority Control Register
address_offset : 0x37C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Clear Enable Control\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite:\n
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ159 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-enable Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-enable Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Clear-enable Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ159 Set-enable Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Software Trigger Interrupt Registers
address_offset : 0xE00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
access : read-write
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