\n

CLK

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x60 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x70 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x40 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKSEL3 (CLKSEL3)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKDIV1 (CLKDIV1)

CLK_CLKDIV2 (CLKDIV2)

CLK_CLKDIV3 (CLKDIV3)

CLK_AHBCLK (AHBCLK)

CLK_PLLCTL (PLLCTL)

CLK_PLL2CTL (PLL2CTL)

CLK_STATUS (STATUS)

CLK_CLKOCTL (CLKOCTL)

CLK_CLKDCTL (CLKDCTL)

CLK_APBCLK0 (APBCLK0)

CLK_APBCLK1 (APBCLK1)


CLK_PWRCTL (PWRCTL)

System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PWRCTL CLK_PWRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTEN LXTEN HIRCEN LIRCEN PDWKDLY PDWKIEN PDWKIF PDEN PDWTCPU DBPDEN

HXTEN : 4~24 MHz External High-Speed Crystal Clock (HXT) Enable Bit (Write Protect)\nThe bit default value is set by flash controller user configuration register config0 [26:24]. \nWhen the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

HXT Disabled

#1 : 1

HXT Enabled

End of enumeration elements list.

LXTEN : 32.768 KHz External Low-Speed Crystal Clock (LXT) Enable Bit (Write Protect)\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

LXT Disabled

#1 : 1

LXT (Normal operation) Enabled

End of enumeration elements list.

HIRCEN : 22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Enable Bit (Write Protect)\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC Disabled

#1 : 1

HIRC Enabled

End of enumeration elements list.

LIRCEN : 10 KHz Internal Low-Speed Oscillator (LIRC) Enable Bit (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

LIRC Disabled

#1 : 1

LIRC Enabled (default 1)

End of enumeration elements list.

PDWKDLY : Wake-Up Delay Counter Enable Bit (Write Protect)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock cycles delay Disabled

#1 : 1

Clock cycles delay Enabled

End of enumeration elements list.

PDWKIEN : Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)\nNote: The interrupt will occur when both PDWKIF and PDWKIEN are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Power-down Mode Wake-up Interrupt Disabled

#1 : 1

Power-down Mode Wake-up Interrupt Enabled

End of enumeration elements list.

PDWKIF : Power-Down Mode Wake-Up Interrupt Status Set by power-down wake-up event , it indicates that resume from Power-down mode The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred Note1: Write 1 to clear the bit to 0. Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-Down Enable Bit (Write Protect)\nWhen this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDWTCPU bit.\n(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set. ( default)\n(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode\nWhen chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next power-down.\nIn Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and LIRC are not controlled by Power-down mode.\nIn Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or the LIRC.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip operating normally or chip in idle mode by WFI command

#1 : 1

Chip enters Power-down mode instant or waits CPU sleep command WFI

End of enumeration elements list.

PDWTCPU : This Bit Control The Power-Down Entry Condition (Write Protect)\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip enters Power-down mode when the PDEN bit is set to 1

#1 : 1

Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction

End of enumeration elements list.

DBPDEN : Chip Entering Power-Down Even ICE Connected\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Chip enters power-down disabled in Debug mode

#1 : 1

Chip enters power-down enabled in Debug mode

End of enumeration elements list.


CLK_CLKSEL0 (CLKSEL0)

Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL0 CLK_CLKSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKSEL STCLKSEL PCLKSEL USBHSEL ICAPSEL SDHSEL

HCLKSEL : HCLK Clock Source Selection (Write Protect) Before clock switching, the related clock sources (both pre-select and new-select) must be turned on The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset. Therefore the default value is either 000b or 111b. These bits are protected bit, it means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PLL clock

#011 : 3

Clock source from LIRC clock

#100 : 4

Clock source from PLL2 clock

#111 : 7

Clock source from HIRC clock

End of enumeration elements list.

STCLKSEL : Cortex-M4 SysTick Clock Source Selection (Write Protect)\n
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from HXT clock/2

#011 : 3

Clock source from HCLK/2

#111 : 7

Clock source from HIRC clock/2

End of enumeration elements list.

PCLKSEL : PCLK Clock Source Selection (Write Protect) These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from HCLK

#1 : 1

Clock source from HCLK/2

End of enumeration elements list.

USBHSEL : USB Host Clock Source Selection (Write Protect) These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL2

#1 : 1

Clock source from PLL

End of enumeration elements list.

ICAPSEL : Image Capture Interface Clock Source Selection These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SDHSEL : SDHOST Engine Clock Source Selection These bits are protected bit. It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.


CLK_CLKSEL1 (CLKSEL1)

Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL1 CLK_CLKSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTSEL EADCSEL SPI0SEL SPI1SEL SPI2SEL SPI3SEL TMR0SEL TMR1SEL TMR2SEL TMR3SEL UARTSEL CLKOSEL WWDTSEL

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bit,and programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from 4~24 MHz external high-speed crystal clock

#01 : 1

Clock source from LXT clock

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from LIRC clock

End of enumeration elements list.

EADCSEL : ADC Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK

End of enumeration elements list.

SPI1SEL : SPI1 Clock Source Selection\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK

End of enumeration elements list.

SPI2SEL : SPI2 Clock Source Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK

End of enumeration elements list.

SPI3SEL : SPI3 Clock Source Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock source from PLL clock

#1 : 1

Clock source from PCLK

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC clock

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC clock

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC clock

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from external trigger

#101 : 5

Clock source from LIRC clock

#111 : 7

Clock source from HIRC clock

End of enumeration elements list.

UARTSEL : UART Clock Source Selection\n
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

End of enumeration elements list.

CLKOSEL : Clock Divider Clock Source Selection\n
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from LXT clock

#10 : 2

Clock source from HCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection\n
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Reserved

#10 : 2

Clock source from HCLK/2048 clock

#11 : 3

Clock source from LIRC clock

End of enumeration elements list.


CLK_CLKSEL2 (CLKSEL2)

Clock Source Select Control Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL2 CLK_CLKSEL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWM0CH01SEL PPWM0CH23SEL PWM0CH45SEL PWM1CH01SEL PWM1CH23SEL PWM1CH45SEL

PWM0CH01SEL : PWM0_0 And PWM0_1 Clock Source Selection\nPWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0] \n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.

PPWM0CH23SEL : PWM0_2 And PWM0_3 Clock Source Selection\nPWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0] \n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.

PWM0CH45SEL : PWM0_4 And PWM0_5 Clock Source Selection PWM0_4 and PWM0_5 used the same Engine clock source both of them use the same prescaler. The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0]
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.

PWM1CH01SEL : PWM1_0 And PWM1_1 Clock Source Selection\nPWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0] \n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.

PWM1CH23SEL : PWM1_2 And PWM1_3 Clock Source Selection\nPWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler. The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0] \n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.

PWM1CH45SEL : PWM1_4 And PWM1_5 Clock Source Selection PWM1_4 and PWM1_5 used the same Engine clock source both of them use the same prescaler. The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0]
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

Clock source from HXT clock

#001 : 1

Clock source from LXT clock

#010 : 2

Clock source from PCLK

#011 : 3

Clock source from HIRC clock

#100 : 4

Clock source from LIRC clock

End of enumeration elements list.


CLK_CLKSEL3 (CLKSEL3)

Clock Source Select Control Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKSEL3 CLK_CLKSEL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0SEL SC1SEL SC2SEL SC3SEL SC4SEL SC5SEL I2S0SEL I2S1SEL

SC0SEL : SC0 Clock Source Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SC1SEL : SC1 Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SC2SEL : SC2 Clock Source Selection\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SC3SEL : SC3 Clock Source Selection\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SC4SEL : SC4 Clock Source Selection\n
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

SC5SEL : SC5 Clock Source Selection\n
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

I2S0SEL : I2S0 Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.

I2S1SEL : I2S1 Clock Source Selection\n
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

Clock source from HXT clock

#01 : 1

Clock source from PLL clock

#10 : 2

Clock source from PCLK

#11 : 3

Clock source from HIRC clock

End of enumeration elements list.


CLK_CLKDIV0 (CLKDIV0)

Clock Divider Number Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV0 CLK_CLKDIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HCLKDIV USBHDIV UARTDIV ADCDIV SDHDIV

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

USBHDIV : USB Host Clock Divide Number From PLL Clock\n
bits : 4 - 7 (4 bit)
access : read-write

UARTDIV : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write

SDHDIV : SDHOST Clock Divide Number From SDHOST Clock Source\n
bits : 24 - 31 (8 bit)
access : read-write


CLK_CLKDIV1 (CLKDIV1)

Clock Divider Number Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV1 CLK_CLKDIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0DIV SC1DIV SC2DIV SC3DIV

SC0DIV : SC0 Clock Divide Number From SC0 Clock Source\n
bits : 0 - 7 (8 bit)
access : read-write

SC1DIV : SC1 Clock Divide Number From SC1 Clock Source\n
bits : 8 - 15 (8 bit)
access : read-write

SC2DIV : SC2 Clock Divide Number From SC2 Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write

SC3DIV : SC3 Clock Divide Number From SC3 Clock Source\n
bits : 24 - 31 (8 bit)
access : read-write


CLK_CLKDIV2 (CLKDIV2)

Clock Divider Number Register 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV2 CLK_CLKDIV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC4DIV SC5DIV

SC4DIV : SC4 Clock Divide Number From SC4 Clock Source\n
bits : 0 - 7 (8 bit)
access : read-write

SC5DIV : SC5 Clock Divide Number From SC5 Clock Source\n
bits : 8 - 15 (8 bit)
access : read-write


CLK_CLKDIV3 (CLKDIV3)

Clock Divider Number Register 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDIV3 CLK_CLKDIV3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPDIV VSENSEDIV EMACDIV

CAPDIV : Image Capture Seneor Clock Divide Number From ICAP Clock Source\n
bits : 0 - 7 (8 bit)
access : read-write

VSENSEDIV : Video Pixel Clock Divide Number From ICAP Clock Source\n
bits : 8 - 15 (8 bit)
access : read-write

EMACDIV : Ethernet Clock Divide Number Form HCLK (NUC472 Only)\n
bits : 16 - 23 (8 bit)
access : read-write


CLK_AHBCLK (AHBCLK)

AHB Devices Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_AHBCLK CLK_AHBCLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMACKEN ISPCKEN EBICKEN USBHCKEN EMACCKEN SDHCKEN CRCCKEN CAPCKEN SENCKEN USBDCKEN CRPTCKEN

PDMACKEN : PDMA Controller Clock Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PDMA engine clock Disabled

#1 : 1

PDMA engine clock Enabled

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Flash ISP engine clock Disabled

#1 : 1

Flash ISP engine clock Enabled

End of enumeration elements list.

EBICKEN : EBI Controller Clock Enable Bit \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

EBI engine clock Disabled

#1 : 1

EBI engine clock Enabled

End of enumeration elements list.

USBHCKEN : USB HOST Controller Clock Enable Bit \n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB HOST engine clock Disabled

#1 : 1

USB HOST engine clock Enabled

End of enumeration elements list.

EMACCKEN : Ethernet Controller Clock Enable Bit (NUC472 Only)\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Ethernet Controller engine clock Disabled

#1 : 1

Ethernet Controller engine clock Enabled

End of enumeration elements list.

SDHCKEN : SDHOST Controller Clock Enable Bit \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

SDHOST engine clock Disabled

#1 : 1

SDHOST engine clock Enabled

End of enumeration elements list.

CRCCKEN : CRC Generator Controller Clock Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

CRC engine clock Disabled

#1 : 1

CRC engine clock Enabled

End of enumeration elements list.

CAPCKEN : Image Capture Interface Controller Clock Enable Bit \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAP controller's clock Disabled

#1 : 1

CAP controller's clock Enabled

End of enumeration elements list.

SENCKEN : Sensor Clock Enable Bit \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Sensor clock Disabled

#1 : 1

Sensor clock Enabled

End of enumeration elements list.

USBDCKEN : USB 2.0 Device Clock Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB device controller's clock Disabled

#1 : 1

USB device controller's clock Enabled

End of enumeration elements list.

CRPTCKEN : Cryptographic Accelerator Clock Enable Bit \n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Cryptographic Accelerator clock Disabled

#1 : 1

Cryptographic Accelerator clock Enabled

End of enumeration elements list.


CLK_PLLCTL (PLLCTL)

PLL Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLLCTL CLK_PLLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBDIV INDIV OUTDV PD BP OE PLLSRC PLLREMAP

FBDIV : PLL Feedback Divider Control Pins\nRefer to the formulas below the table.
bits : 0 - 8 (9 bit)
access : read-write

INDIV : PLL Input Divider Control Pins\nRefer to the formulas below the table.
bits : 9 - 13 (5 bit)
access : read-write

OUTDV : PLL Output Divider Control Pins\nRefer to the formulas below the table.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-Down Mode\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode

#1 : 1

PLL is in Power-down mode (default)

End of enumeration elements list.

BP : PLL Bypass Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL is in normal mode (default)

#1 : 1

PLL clock output is same as clock input (XTALin)

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL FOUT Enabled

#1 : 1

PLL FOUT is fixed low

End of enumeration elements list.

PLLSRC : PLL Source Clock Selection\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL source clock from HXT

#1 : 1

PLL source clock from HIRC

End of enumeration elements list.

PLLREMAP : PLL Remap Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PLL remap enable

#1 : 1

PLL remap disable

End of enumeration elements list.


CLK_PLL2CTL (PLL2CTL)

PLL2 Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PLL2CTL CLK_PLL2CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL2DIV PLL2CKEN

PLL2DIV : PLL2 Divider Control Note: Max. PLL2 frequency is 240 MHz when HXT is1 2 MHz.
bits : 0 - 7 (8 bit)
access : read-write

PLL2CKEN : USB PHY 480 MHz Enable Bit\nThis bit enables USB PHY PLL (480 MHz), and user needs to care the extenal crystal is 12 MHz or 24 MHz source.\nNote: Refer to OTG_PHYCTL[8] register to set the exteranl crystal frequency HXT.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB PHY PLL (480 MHz) Disabled

#1 : 1

USB PHY PLL (480 MHz) Enabled

End of enumeration elements list.


CLK_STATUS (STATUS)

Clock Status Monitor Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_STATUS CLK_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HXTSTB LXTSTB PLLSTB LIRCSTB HIRCSTB PLL2STB CLKSFAIL

HXTSTB : 4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

HXT clock is not stable or disabled

#1 : 1

HXT clock is stable

End of enumeration elements list.

LXTSTB : 32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag\nNote: This is read only.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

LXT clock is not stable or disabled

#1 : 1

LXT clock is stabled

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag\nNote: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal PLL clock is not stable or disabled

#1 : 1

Internal PLL clock is stable

End of enumeration elements list.

LIRCSTB : 10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

LIRC clock is not stable or disabled

#1 : 1

LIRC clock is stable

End of enumeration elements list.

HIRCSTB : 22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag\nNote: This bit is read only.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

HIRC clock is not stable or disabled

#1 : 1

HIRC clock is stable

End of enumeration elements list.

PLL2STB : Internal PLL2 Clock Source Stable Flag\nNote: This bit is read only.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Internal PLL2 clock is not stable or disabled

#1 : 1

Internal PLL2 clock is stable

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag\nNote1: This bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote2: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock switching success

#1 : 1

Clock switching failure

End of enumeration elements list.


CLK_CLKOCTL (CLKOCTL)

Frequency Divider Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKOCTL CLK_CLKOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSEL CLKOEN DIV1EN

FSEL : Divider Output Frequency Selection\nThe formula of output frequency is:\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clock output disabled

#1 : 1

Clock output enabled

End of enumeration elements list.

DIV1EN : Frequency Divider 1 Enable Bit \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Divider output frequency is dependent on FSEL value when FDIVEN is enabled

#1 : 1

Divider output frequency is input clock frequency

End of enumeration elements list.


CLK_CLKDCTL (CLKDCTL)

Clock Fail Detector Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CLKDCTL CLK_CLKDCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSFDEN SYSFIEN SYSFIF IRCDEN IRCFIEN IRCFIF

SYSFDEN : System Clock Detector Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

system clock fail interrupt disabled

#1 : 1

system clock fail interrupt enabled

End of enumeration elements list.

SYSFIEN : System Clock Detector Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

system clock fail interrupt disabled

#1 : 1

system clock fail interrupt enabled

End of enumeration elements list.

SYSFIF : System Clock Detect Fail Flag\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

System clock normal

#1 : 1

System clock abnormal (write 1 to clear)

End of enumeration elements list.

IRCDEN : Internal RC Clock Detector Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC clock fail interrupt disabled

#1 : 1

IRC clock fail interrupt enabled

End of enumeration elements list.

IRCFIEN : Internal RC Clock Detector Interrupt Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC clock fail interrupt disabled

#1 : 1

IRC clock fail interrupt enabled

End of enumeration elements list.

IRCFIF : Internal RC Clock Fail Flag\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

IRC clock normal

#1 : 1

IRC abnormal (write 1 to clear)

End of enumeration elements list.


CLK_APBCLK0 (APBCLK0)

APB Devices Clock Enable Control Register 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK0 CLK_APBCLK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCKEN RTCCKEN TMR0CKEN TMR1CKEN TMR2CKEN TMR3CKEN FDIVCKEN ACMPCKEN I2C0CKEN I2C1CKEN I2C2CKEN I2C3CKEN SPI0CKEN SPI1CKEN SPI2CKEN SPI3CKEN UART0CKEN UART1CKEN UART2CKEN UART3CKEN UART4CKEN UART5CKEN CAN0CKEN CAN1CKEN OTGCKEN ADCCKEN I2S0CKEN I2S1CKEN PS2CKEN

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect) This bit is the protected bit, which means programming this needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog Timer Clock Disabled

#1 : 1

Watchdog Timer Clock Enabled

End of enumeration elements list.

RTCCKEN : Real-Time-Clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Clock Disabled

#1 : 1

RTC Clock Enabled

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer0 Clock Disabled

#1 : 1

Timer0 Clock Enabled

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer1 Clock Disabled

#1 : 1

Timer1 Clock Enabled

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer2 Clock Disabled

#1 : 1

Timer2 Clock Enabled

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Timer3 Clock Disabled

#1 : 1

Timer3 Clock Enabled

End of enumeration elements list.

FDIVCKEN : Frequency Divider Output Clock Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

FDIV Clock Disabled

#1 : 1

FDIV Clock Enabled

End of enumeration elements list.

ACMPCKEN : Analog Comparator Clock Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Analog Comparator Clock Disabled

#1 : 1

Analog Comparator Clock Enabled

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C0 Clock Disabled

#1 : 1

I2C0 Clock Enabled

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C1 Clock Disabled

#1 : 1

I2C1 Clock Enabled

End of enumeration elements list.

I2C2CKEN : I2C2 Clock Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C2 Clock Disabled

#1 : 1

I2C2 Clock Enabled

End of enumeration elements list.

I2C3CKEN : I2C3 Clock Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C3 Clock Disabled

#1 : 1

I2C3 Clock Enabled

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI0 Clock Disabled

#1 : 1

SPI0 Clock Enabled

End of enumeration elements list.

SPI1CKEN : SPI1 Clock Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI1 Clock Disabled

#1 : 1

SPI1 Clock Enabled

End of enumeration elements list.

SPI2CKEN : SPI2 Clock Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI2 Clock Disabled

#1 : 1

SPI2 Clock Enabled

End of enumeration elements list.

SPI3CKEN : SPI3 Clock Enable Bit \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPI3 Clock Disabled

#1 : 1

SPI3 Clock Enabled

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART0 clock Disabled

#1 : 1

UART0 clock Enabled

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART1 clock Disabled

#1 : 1

UART1 clock Enabled

End of enumeration elements list.

UART2CKEN : UART2 Clock Enable Bit \n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART2 clock Disabled

#1 : 1

UART2 clock Enabled

End of enumeration elements list.

UART3CKEN : UART3 Clock Enable Bit \n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART3 clock Disabled

#1 : 1

UART3 clock Enabled

End of enumeration elements list.

UART4CKEN : UART4 Clock Enable Bit \n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART4 clock Disabled

#1 : 1

UART4 clock Enabled

End of enumeration elements list.

UART5CKEN : UART5 Clock Enable Bit \n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

UART5 clock Disabled

#1 : 1

UART5 clock Enabled

End of enumeration elements list.

CAN0CKEN : CAN Bus Controller-0 Clock Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAN0 clock Disabled

#1 : 1

CAN0 clock Enabled

End of enumeration elements list.

CAN1CKEN : CAN Bus Controller-1 Clock Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

CAN1 clock Disabled

#1 : 1

CAN1 clock Enabled

End of enumeration elements list.

OTGCKEN : USB 2.0 OTG Device Controller Clock Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

OTG clock Disabled

#1 : 1

OTG clock Enabled

End of enumeration elements list.

ADCCKEN : Analog-Digital-Converter (ADC) Clock Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

ADC clock Disabled

#1 : 1

ADC clock Enabled

End of enumeration elements list.

I2S0CKEN : I2S0 Clock Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S Clock Disabled

#1 : 1

I2S Clock Enabled

End of enumeration elements list.

I2S1CKEN : I2S1 Clock Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2S1 Clock Disabled

#1 : 1

I2S1 Clock Enabled

End of enumeration elements list.

PS2CKEN : PS/2 Clock Enable Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PS/2 clock Disabled

#1 : 1

PS/2 clock Enabled

End of enumeration elements list.


CLK_APBCLK1 (APBCLK1)

APB Devices Clock Enable Control Register 1
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_APBCLK1 CLK_APBCLK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SC0CKEN SC1CKEN SC2CKEN SC3CKEN SC4CKEN SC5CKEN I2C4CKEN PWM0CH01CKEN PWM0CH23CKEN PWM0CH45CKEN PWM1CH01CKEN PWM1CH23CKEN PWM1CH45CKEN QEI0CKEN QEI1CKEN ECAP0CKEN ECAP1CKEN EPWM0CKEN EPWM1CKEN OPACKEN EADCCKEN

SC0CKEN : SC0 Clock Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC0 Clock Disabled

#1 : 1

SC0 Clock Enabled

End of enumeration elements list.

SC1CKEN : SC1 Clock Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC1 Clock Disabled

#1 : 1

SC1 Clock Enabled

End of enumeration elements list.

SC2CKEN : SC2 Clock Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC2 Clock Disabled

#1 : 1

SC2 Clock Enabled

End of enumeration elements list.

SC3CKEN : SC3 Clock Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC3 Clock Disabled

#1 : 1

SC3 Clock Enabled

End of enumeration elements list.

SC4CKEN : SC4 Clock Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC4 Clock Disabled

#1 : 1

SC4 Clock Enabled

End of enumeration elements list.

SC5CKEN : SC5 Clock Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

SC5 Clock Disabled

#1 : 1

SC5 Clock Enabled

End of enumeration elements list.

I2C4CKEN : I2C4 Clock Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C4 Clock Disabled

#1 : 1

I2C4 Clock Enabled

End of enumeration elements list.

PWM0CH01CKEN : PWM0_01 Clock Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_01 Clock Disabled

#1 : 1

PWM0_01 Clock Enabled

End of enumeration elements list.

PWM0CH23CKEN : PWM0_23 Clock Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_23 Clock Disabled

#1 : 1

PWM0_23 Clock Enabled

End of enumeration elements list.

PWM0CH45CKEN : PWM0_45 Clock Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM0_45 Clock Disabled

#1 : 1

PWM0_45 Clock Enabled

End of enumeration elements list.

PWM1CH01CKEN : PWM1_01 Clock Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM1_01 Clock Disabled

#1 : 1

PWM1_01 Clock Enabled

End of enumeration elements list.

PWM1CH23CKEN : PWM1_23 Clock Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM1_23 Clock Disabled

#1 : 1

PWM1_23 Clock Enabled

End of enumeration elements list.

PWM1CH45CKEN : PWM1_45 Clock Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM1_45 Clock Disabled

#1 : 1

PWM1_45 Clock Enabled

End of enumeration elements list.

QEI0CKEN : Quadrature Encoder Interface (QEI0) Clock Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI0 clock Disabled

#1 : 1

QEI0 clock Enabled

End of enumeration elements list.

QEI1CKEN : Quadrature Encoder Interface (QEI1) Clock Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

QEI1 clock Disabled

#1 : 1

QEI1 clock Enabled

End of enumeration elements list.

ECAP0CKEN : Enhanced CAP (ECAP0) Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP0 clock Disabled

#1 : 1

ECAP0 clock Enabled

End of enumeration elements list.

ECAP1CKEN : Enhanced CAP (ECAP1) Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

ECAP1 clock Disabled

#1 : 1

ECAP1 clock Enabled

End of enumeration elements list.

EPWM0CKEN : Enhanced PWM0 (EPWM) Clock Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM0 clock Disabled

#1 : 1

EPWM0 clock Enabled

End of enumeration elements list.

EPWM1CKEN : Enhanced PWM1 (EPWM) Clock Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

EPWM1 clock Disabled

#1 : 1

EPWM1 clock Enabled

End of enumeration elements list.

OPACKEN : OP Amplifier (OPA) Clock Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

OPA clock Disabled

#1 : 1

OPA clock Enabled

End of enumeration elements list.

EADCCKEN : Enhanced Analog-Digital-Converter (E ADC) Clock Enable Bit\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

EADC clock Disabled

#1 : 1

EADC clock Enabled

End of enumeration elements list.



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