FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBA (DFBA)

FMC_FTCTL (FTCTL)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_ISPDAT (ISPDAT)

FMC_MPDAT0 (MPDAT0)

FMC_MPDAT1 (MPDAT1)

FMC_MPDAT2 (MPDAT2)

FMC_MPDAT3 (MPDAT3)

FMC_ISPCMD (ISPCMD)

FMC_MPSTS (MPSTS)

FMC_MPADDR (MPADDR)

ISPEN : ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Config-Bits Update By ISP Enable Bit (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.\nNote: This bit needs to be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x4000_0100 to disable register protection. Refer to the register SYS_REGLCTL at address GCR_BA+0x100
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address\nThis register indicates data flash start address. It is a read only register.\nThe data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1.
bits : 0 - 31 (32 bit)
access : read-only

FOM : Frequency Optimization Mode (Write Protect)\n
bits : 4 - 6 (3 bit)
access : read-write

ISPADDR : ISP Address\nThe NUC442/NUC472 series is equipped with an embedded flash and supports word program only. ISPADDR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP Busy Flag\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Chip Boot Selection Mode This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
bits : 1 - 2 (2 bit)
access : read-only

ISPFF : ISP Fail Flag (Read Only)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Destination address is illegal, such as over an available range.
bits : 6 - 6 (1 bit)
access : read-only

VECMAP : Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_07FF is mapping to address {VECMAP[11:2], 11'h000} ~ {VECMAP[11:2], 11'h7FF}\nVECMAP[1:0] is needed to set 0.
bits : 9 - 20 (12 bit)
access : read-only

CFGCRCF : User-Configuration CRC Check Flag (Read Only)\nThis bit is set by hardware when detecting CONFIG CRC checksum is error\n
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT0 : ISP Data 0\nThis register is the first 32-bit data for 32b/64b/multi-word program, and it is also the mirror of FMC_ISPDAT register, both registers keep the same data.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT1 : ISP Data 1\nThis register is the second 32-bit data for 32b/64b/multi-word program.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT2 : ISP Data 2\nThis register is the third 32-bit data for 32b/64b/multi-word program.
bits : 0 - 31 (32 bit)
access : read-write

ISPDAT3 : ISP Data 3\nThis register is the fourth 32-bit data for 32b/64b/multi-word program.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP Command\nPlease check the table below for ISP commands.
bits : 0 - 5 (6 bit)
access : read-write

MPBUSY : ISP Multi-Word Program Busy Flag (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Read Only)\nThis bit is set when ISP Multi-Word Program operation failed.
bits : 2 - 2 (1 bit)
access : read-only

D0 : ISP DATA 0 Flag (Read Only)\nThis bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 is programmed to flash complete.\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D1 : ISP DATA 1 Flag (Read Only)\nThis bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 is programmed to flash complete.\n
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D2 : ISP DATA 2 Flag (Read Only)\nThis bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 is programmed to flash complete.\n
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

D3 : ISP DATA 3 Flag (Read Only)\nThis bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 is programmed to flash complete.\n
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MPADDR : ISP Multi-Word Program Address Status\nMPADDR is the address of ISP Multi-Word Program operation when MPBUSY flag is 1. MPADDR will keep the final address when Multi-Word Program is aborted or finished.
bits : 0 - 31 (32 bit)
access : read-only