\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKDIV : External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as below:\nNote: Default value of output clock is HCLK/1
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
HCLK/1
#001 : 1
HCLK/2
#010 : 2
HCLK/4
#011 : 3
HCLK/8.\nDefault
#100 : 4
HCLK/16
#101 : 5
HCLK/32
End of enumeration elements list.
CRYPTOEN : Encrypt/Decrypt Function Enable Bits (For 4 Individual Chip Select)\n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : 0
Encrypt/Decrypt function Disabled
1 : 1
Encrypt/Decrypt function Enabled
End of enumeration elements list.
CSPOLINV : Reverse Chip Select\n
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : 0
nCS (chip select active low)
1 : 1
CS (chip select active high)
End of enumeration elements list.
External Bus Interface Bank3 Timing Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TALE : Bank3 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
bits : 0 - 2 (3 bit)
access : read-write
TACC : EBI Bank3 Data Access Time\nTACC define data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write
TAHD : EBI Bank3 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
W2X : Bank3 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[3] return to high if W2X is not zero.\n0 : reserved.
bits : 12 - 15 (4 bit)
access : read-write
R2W : Bank3 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[3] return to high if R2W is not zero.\n0 : reserved.
bits : 16 - 19 (4 bit)
access : read-write
R2R : Bank3 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[3] return to high if R2R is not zero.\n0 : reserved.
bits : 24 - 27 (4 bit)
access : read-write
CSEN : EBI Bank3 Enable Bit\nThis bit is the functional enable bit for EBI.\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
DW16 : EBI Bank3 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
SEPEN : EBI Bank3 Address/Data Bus Separating Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address/Data Bus Separating Disabled
#1 : 1
Address/Data Bus Separating Enabled
End of enumeration elements list.
External Bus Interface Crypto Key Word 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Crypto Key Word 0 (key[31:0]).
bits : 0 - 31 (32 bit)
access : read-write
External Bus Interface Crypto Key Word 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Crypto Key Word 1 (key[63:32]).
bits : 0 - 31 (32 bit)
access : read-write
External Bus Interface Crypto Key Word 2
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Crypto Key Word 2 (key[95:64]).
bits : 0 - 31 (32 bit)
access : read-write
External Bus Interface Crypto Key Word 3
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Crypto Key Word 3 (key[127:96]).
bits : 0 - 31 (32 bit)
access : read-write
External Bus Interface Bank0 Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TALE : Bank0 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
bits : 0 - 2 (3 bit)
access : read-write
TACC : EBI Bank0 Data Access Time\nTACC define data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write
TAHD : EBI Bank0 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
W2X : Bank0 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
R2W : Bank0 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero.\n
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
R2R : Bank0 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero.\n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
CSEN : EBI Bank0 Enable Bit\nThis bit is the functional enable bit for EBI.\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
DW16 : EBI Bank0 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
SEPEN : EBI Bank0 Address/Data Bus Separating Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address/Data Bus Separating Disabled
#1 : 1
Address/Data Bus Separating Enabled
End of enumeration elements list.
External Bus Interface Bank1 Timing Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TALE : Bank1 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
bits : 0 - 2 (3 bit)
access : read-write
TACC : EBI Bank1 Data Access Time\nTACC define data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write
TAHD : EBI Bank1 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
W2X : Bank1 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[1] return to high if W2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
R2W : Bank1 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[1] return to high if R2W is not zero.\n
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
R2R : Bank1 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[1] return to high if R2R is not zero.\n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
CSEN : EBI Bank1 Enable Bit\nThis bit is the functional enable bit for EBI.\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
DW16 : EBI Bank1 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
SEPEN : EBI Bank1 Address/Data Bus Separating Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address/Data Bus Separating Disabled
#1 : 1
Address/Data Bus Separating Enabled
End of enumeration elements list.
External Bus Interface Bank2 Timing Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TALE : Bank2 Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by TALE.\n
bits : 0 - 2 (3 bit)
access : read-write
TACC : EBI Bank2 Data Access Time\nTACC define data access time (tACC).\n
bits : 3 - 7 (5 bit)
access : read-write
TAHD : EBI Bank2 Data Access Hold Time\nTAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
W2X : Bank2 Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS[2] return to high if W2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
0 : 0
reserved
End of enumeration elements list.
R2W : Bank2 Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS[2] return to high if R2W is not 0.\n
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0 : 0
Reserved
End of enumeration elements list.
R2R : Bank2 Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS[2] return to high if R2R is not 0.\n
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0 : 0
Reserved
End of enumeration elements list.
CSEN : EBI Bank2 Enable Bit\nThis bit is the functional enable bit for EBI.\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function Disabled
#1 : 1
EBI function Enabled
End of enumeration elements list.
DW16 : EBI Bank2 Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
SEPEN : EBI Bank2 Address/Data Bus Separating Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Address/Data Bus Separating Disabled
#1 : 1
Address/Data Bus Separating Enabled
End of enumeration elements list.
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