GPIO

PIN0 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : Port N Bit M Pin Value\nEach bit of the register reflects the actual status of the respective port pin. If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
bits : 15 - 15 (1 bit)
access : read-only

PE_MODE

PE I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DINOFF

PE Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DOUT

PE Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DATMSK

PE Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_PIN

PE Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_DBEN

PE De-bounce Enable Control
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTTYPE

PE Interrupt Trigger Type Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTEN

PE Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_INTSRC

PE Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_SMTEN

PE Input Schmitt Trigger Enable
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE_SLEWCTL

PE High Slew Rate Control
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DBEN

PA De-bounce Enable Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBEN0 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN1 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN2 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN3 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN4 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN5 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN6 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN7 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN8 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN9 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN10 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN11 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN12 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN13 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN14 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

DBEN15 : Port N Bit M Input De-Bounce Enable DBEN[m] is used to enable the de-bounce function for each corresponding bit. DBEN[m] is valid for edge-triggered interrupt only and is ignored for level triggered interrupt. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock is controlled by GPIO_DBCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m input de-bounce Disabled

#1 : 1

Port n bit m input de-bounce Enabled

End of enumeration elements list.

PF_MODE

PF I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DINOFF

PF Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DOUT

PF Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DATMSK

PF Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_PIN

PF Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_DBEN

PF De-bounce Enable Control
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTTYPE

PF Interrupt Trigger Type Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTEN

PF Interrupt Enable
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_INTSRC

PF Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_SMTEN

PF Input Schmitt Trigger Enable
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF_SLEWCTL

PF High Slew Rate Control
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTTYPE

PA Interrupt Trigger Type Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE0 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE1 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE2 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE3 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE4 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE5 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE6 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE7 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE8 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE9 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE10 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE11 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE12 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE13 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE14 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

TYPE15 : Port N Bit M Edge Or Level Triggered Interrupt Control\nTYPE[m] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\nNote1: If pin is set as the level trigger interrupt, only one level can be set on the registers Pn_INTEN. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.\nNote2: The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge triggered interrupt

#1 : 1

Level triggered interrupt

End of enumeration elements list.

PG_MODE

PG I/O Mode Control
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_DINOFF

PG Digital Input Path Disable Control
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_DOUT

PG Data Output Value
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_DATMSK

PG Data Output Write Mask
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_PIN

PG Pin Value
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_DBEN

PG De-bounce Enable Control
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_INTTYPE

PG Interrupt Trigger Type Register
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_INTEN

PG Interrupt Enable
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_INTSRC

PG Interrupt Source Flag
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_SMTEN

PG Input Schmitt Trigger Enable
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG_SLEWCTL

PG High Slew Rate Control
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTEN

PA Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLIEN0 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN1 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN2 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN3 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN4 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN5 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN6 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN7 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN8 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN9 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN10 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN11 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN12 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN13 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN14 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

FLIEN15 : Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input\nFLIEN[n] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m low-level or falling edge interrupt Disabled

#1 : 1

Port n bit m low-level or falling edge interrupt Enabled

End of enumeration elements list.

RHIEN0 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN1 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN2 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN3 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN4 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN5 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN6 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN7 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN8 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN9 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN10 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN11 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN12 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN13 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN14 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

RHIEN15 : Port N Bit M Interrupt Enable For Rising Edge Or High Level Input\nRHIEN[m] enables the interrupt for each of the corresponding input of Port n. Setting this bit to 1 also enables the pin wake-up function.\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Port n bit m high-level or rising edge interrupt Disabled

#1 : 1

Port n bit m high-level or rising edge interrupt Enabled

End of enumeration elements list.

PH_MODE

PH I/O Mode Control
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_DINOFF

PH Digital Input Path Disable Control
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_DOUT

PH Data Output Value
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_DATMSK

PH Data Output Write Mask
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_PIN

PH Pin Value
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_DBEN

PH De-bounce Enable Control
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_INTTYPE

PH Interrupt Trigger Type Register
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_INTEN

PH Interrupt Enable
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_INTSRC

PH Interrupt Source Flag
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_SMTEN

PH Input Schmitt Trigger Enable
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH_SLEWCTL

PH High Slew Rate Control
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTSRC

PA Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTSRC0 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC1 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC2 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC3 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC4 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC5 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC6 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC7 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC8 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC9 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC10 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC11 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC12 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC13 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC14 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

INTSRC15 : Port N Bit M Interrupt Trigger Source Indicator\nRead:\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

No interrupt at Port n.\nNo effect

#1 : 1

Port n bit m generate an interrupt.\nClear the correspond pending interrupt

End of enumeration elements list.

PI_MODE

PI I/O Mode Control
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_DINOFF

PI Digital Input Path Disable Control
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_DOUT

PI Data Output Value
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_DATMSK

PI Data Output Write Mask
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_PIN

PI Pin Value
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_DBEN

PI De-bounce Enable Control
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_INTTYPE

PI Interrupt Trigger Type Register
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_INTEN

PI Interrupt Enable
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_INTSRC

PI Interrupt Source Flag
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_SMTEN

PI Input Schmitt Trigger Enable
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI_SLEWCTL

PI High Slew Rate Control
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_SMTEN

PA Input Schmitt Trigger Enable
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMTEN0 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN1 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN2 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN3 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN4 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN5 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN6 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN7 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN8 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN9 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN10 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN11 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN12 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN13 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN14 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

SMTEN15 : Port N Bit M Input Schmitt Trigger Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O input Schmitt Trigger function Disabled

#1 : 1

P I/O input Schmitt Trigger function Enabled

End of enumeration elements list.

PA_SLEWCTL

PA High Slew Rate Control
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSREN0 : Port N Bit M High Slew Rate Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN1 : Port N Bit M High Slew Rate Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN2 : Port N Bit M High Slew Rate Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN3 : Port N Bit M High Slew Rate Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN4 : Port N Bit M High Slew Rate Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN5 : Port N Bit M High Slew Rate Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN6 : Port N Bit M High Slew Rate Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN7 : Port N Bit M High Slew Rate Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN8 : Port N Bit M High Slew Rate Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN9 : Port N Bit M High Slew Rate Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN10 : Port N Bit M High Slew Rate Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN11 : Port N Bit M High Slew Rate Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN12 : Port N Bit M High Slew Rate Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN13 : Port N Bit M High Slew Rate Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN14 : Port N Bit M High Slew Rate Control\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

HSREN15 : Port N Bit M High Slew Rate Control\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

P I/O output with basic slew rate

#1 : 1

P I/O output with higher slew rate

End of enumeration elements list.

PA_DINOFF

PA Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DINOFF0 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF1 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF2 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF3 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF4 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF5 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF6 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF7 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF8 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF9 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF10 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF11 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF12 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF13 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF14 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

DINOFF15 : Port N Bit M Off Digital Input Path\nEach of these bits is used to turn off the digital input path of port n bit m pin. If input is analog signal, users can turn off digital input path to avoid input current leakage.\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

Digital input path Enabled

#1 : 1

Digital input path Disabled (Digital input is tied to low)

End of enumeration elements list.

PB_MODE

PB I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DINOFF

PB Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_DBCTL (DBCTL)

Interrupt De-bounce Control
address_offset : 0x440 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBCLKSEL : De-Bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

Sample interrupt input once per 1 clocks

#0001 : 1

Sample interrupt input once per 2 clocks

#0010 : 2

Sample interrupt input once per 4 clocks

#0011 : 3

Sample interrupt input once per 8 clocks

#0100 : 4

Sample interrupt input once per 16 clocks

#0101 : 5

Sample interrupt input once per 32 clocks

#0110 : 6

Sample interrupt input once per 64 clocks

#0111 : 7

Sample interrupt input once per 128 clocks

#1000 : 8

Sample interrupt input once per 256 clocks

#1001 : 9

Sample interrupt input once per 2*256 clocks

#1010 : 10

Sample interrupt input once per 4*256 clocks

#1011 : 11

Sample interrupt input once per 8*256 clocks

#1100 : 12

Sample interrupt input once per 16*256 clocks

#1101 : 13

Sample interrupt input once per 32*256 clocks

#1110 : 14

Sample interrupt input once per 64*256 clocks

#1111 : 15

Sample interrupt input once per 128*256 clocks

End of enumeration elements list.

DBCLKSRC : De-Bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is the HCLK

#1 : 1

De-bounce counter clock source is the internal 10 kHz clock

End of enumeration elements list.

ICLKON : Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the clock if the all port interrupts are disabled

#1 : 1

Interrupt generated circuit clock always Enabled

End of enumeration elements list.

PB_DOUT

PB Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DATMSK

PB Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_PIN

PB Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DBEN

PB De-bounce Enable Control
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTTYPE

PB Interrupt Trigger Type Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTEN

PB Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTSRC

PB Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_SMTEN

PB Input Schmitt Trigger Enable
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_SLEWCTL

PB High Slew Rate Control
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DOUT

PA Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUT0 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT1 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT2 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT3 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT4 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT5 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT6 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT7 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT8 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT9 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT10 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT11 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT12 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT13 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT14 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

DOUT15 : Port N Bit M Output\nEach of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Drive port n bit m high low

#1 : 1

Drive port n bit m high level

End of enumeration elements list.

PC_MODE

PC I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA0_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDIO : Port N Bit M (PDIO) Value\nWrite:\nFor example, a writing of PA0 reflects the value of bit PA_DOUT[0], a reading returns the value of PA_PIN[0].
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Clear PDIO port latch to output low.\nPort pin of PDIO is a low level

#1 : 1

Set PDIO port latch to output high.\nPort pin of PDIO is a high level

End of enumeration elements list.

PA1_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA2_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA3_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA4_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA5_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA6_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA7_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA8_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA9_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA10_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA11_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x82C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA12_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA13_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA14_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA15_PDIO

GPIO PA.n Pin Data Input/Output
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DINOFF

PC Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB0_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB1_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB2_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x848 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB3_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x84C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB4_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB5_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB6_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB7_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB8_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB9_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB10_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB11_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB12_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB13_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB14_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x878 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB15_PDIO

GPIO PB.n Pin Data Input/Output
address_offset : 0x87C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DOUT

PC Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC0_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x880 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC1_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x884 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC2_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x888 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC3_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x88C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC4_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x890 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC5_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x894 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC6_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x898 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC7_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x89C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC8_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC9_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC10_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC11_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC12_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC13_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC14_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC15_PDIO

GPIO PC.n Pin Data Input/Output
address_offset : 0x8BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DATMSK

PC Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD0_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD1_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD2_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD3_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD4_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD5_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD6_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD7_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD8_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD9_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD10_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD11_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD12_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD13_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD14_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD15_PDIO

GPIO PD.n Pin Data Input/Output
address_offset : 0x8FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_PIN

PC Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE0_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE1_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE2_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x908 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE3_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x90C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE4_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x910 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE5_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x914 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE6_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x918 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE7_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x91C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE8_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x920 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE9_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x924 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE10_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x928 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE11_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x92C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE12_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x930 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE13_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x934 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE14_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x938 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PE15_PDIO

GPIO PE.n Pin Data Input/Output
address_offset : 0x93C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_DBEN

PC De-bounce Enable Control
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF0_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x940 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF1_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x944 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF2_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x948 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF3_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x94C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF4_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x950 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF5_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x954 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF6_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x958 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF7_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x95C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF8_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x960 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF9_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x964 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF10_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x968 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF11_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x96C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF12_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x970 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF13_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x974 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF14_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x978 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PF15_PDIO

GPIO PF.n Pin Data Input/Output
address_offset : 0x97C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTTYPE

PC Interrupt Trigger Type Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG0_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x980 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG1_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x984 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG2_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x988 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG3_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x98C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG4_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x990 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG5_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x994 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG6_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x998 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG7_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x99C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG8_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG9_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG10_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG11_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG12_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG13_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG14_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PG15_PDIO

GPIO PG.n Pin Data Input/Output
address_offset : 0x9BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTEN

PC Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH0_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH1_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH2_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH3_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH4_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH5_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH6_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH7_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH8_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH9_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH10_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH11_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH12_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH13_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH14_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PH15_PDIO

GPIO PH.n Pin Data Input/Output
address_offset : 0x9FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_INTSRC

PC Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI0_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI1_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI2_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI3_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI4_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI5_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI6_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI7_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI8_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI9_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI10_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI11_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI12_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI13_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI14_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PI15_PDIO

GPIO PI.n Pin Data Input/Output
address_offset : 0xA3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_SMTEN

PC Input Schmitt Trigger Enable
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC_SLEWCTL

PC High Slew Rate Control
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DATMSK

PA Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATMSK0 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK1 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK2 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK3 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK4 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK5 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK6 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK7 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK8 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK9 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK10 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK11 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK12 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK13 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK14 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

DATMSK15 : Port N Bit M Data Output Write Mask\nThese bits are used to protect the corresponding register of Pn_DOUT[m]. When set the DATMSK [m] to 1, the writing to Pn_DOUT[m] bit is ignored. The write to port pin latch is masked.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pn_DOUT[m] bit writing is valid

#1 : 1

Pn_DOUT[m] bit writing is ignored

End of enumeration elements list.

PD_MODE

PD I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DINOFF

PD Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DOUT

PD Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DATMSK

PD Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_PIN

PD Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_DBEN

PD De-bounce Enable Control
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTTYPE

PD Interrupt Trigger Type Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTEN

PD Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_INTSRC

PD Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_SMTEN

PD Input Schmitt Trigger Enable
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PD_SLEWCTL

PD High Slew Rate Control
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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ChipSelect

GPIO

Peripheral Memory Blocks

Registers

PA_MODE

PA_PIN

PE_MODE

PE_DINOFF

PE_DOUT

PE_DATMSK

PE_PIN

PE_DBEN

PE_INTTYPE

PE_INTEN

PE_INTSRC

PE_SMTEN

PE_SLEWCTL

PA_DBEN

PF_MODE

PF_DINOFF

PF_DOUT

PF_DATMSK

PF_PIN

PF_DBEN

PF_INTTYPE

PF_INTEN

PF_INTSRC

PF_SMTEN

PF_SLEWCTL

PA_INTTYPE

PG_MODE

PG_DINOFF

PG_DOUT

PG_DATMSK

PG_PIN

PG_DBEN

PG_INTTYPE

PG_INTEN

PG_INTSRC

PG_SMTEN

PG_SLEWCTL

PA_INTEN

PH_MODE

PH_DINOFF

PH_DOUT

PH_DATMSK

PH_PIN

PH_DBEN

PH_INTTYPE

PH_INTEN

PH_INTSRC

PH_SMTEN

PH_SLEWCTL

PA_INTSRC

PI_MODE

PI_DINOFF

PI_DOUT

PI_DATMSK

PI_PIN

PI_DBEN

PI_INTTYPE

PI_INTEN

PI_INTSRC

PI_SMTEN

PI_SLEWCTL

PA_SMTEN

PA_SLEWCTL

PA_DINOFF

PB_MODE

PB_DINOFF

GPIO_DBCTL (DBCTL)

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PB_SMTEN

PB_SLEWCTL