\n

PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x400 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x480 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x43C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PDMA_DSCT0_CTL (DSCT0_CTL)

PDMA_DSCT1_CTL (DSCT1_CTL)

PDMA_CURSCAT0 (CURSCAT0)

PDMA_CURSCAT1 (CURSCAT1)

PDMA_CURSCAT2 (CURSCAT2)

PDMA_CURSCAT3 (CURSCAT3)

PDMA_CURSCAT4 (CURSCAT4)

PDMA_CURSCAT5 (CURSCAT5)

PDMA_CURSCAT6 (CURSCAT6)

PDMA_CURSCAT7 (CURSCAT7)

PDMA_CURSCAT8 (CURSCAT8)

PDMA_CURSCAT9 (CURSCAT9)

PDMA_CURSCAT10 (CURSCAT10)

PDMA_CURSCAT11 (CURSCAT11)

PDMA_CURSCAT12 (CURSCAT12)

PDMA_CURSCAT13 (CURSCAT13)

PDMA_CURSCAT14 (CURSCAT14)

PDMA_CURSCAT15 (CURSCAT15)

PDMA_DSCT1_ENDSA (DSCT1_ENDSA)

PDMA_DSCT1_ENDDA (DSCT1_ENDDA)

PDMA_DSCT1_NEXT (DSCT1_NEXT)

PDMA_DSCT2_CTL (DSCT2_CTL)

PDMA_DSCT2_ENDSA (DSCT2_ENDSA)

PDMA_DSCT2_ENDDA (DSCT2_ENDDA)

PDMA_DSCT2_NEXT (DSCT2_NEXT)

PDMA_DSCT3_CTL (DSCT3_CTL)

PDMA_DSCT3_ENDSA (DSCT3_ENDSA)

PDMA_DSCT3_ENDDA (DSCT3_ENDDA)

PDMA_DSCT3_NEXT (DSCT3_NEXT)

PDMA_DSCT0_ENDSA (DSCT0_ENDSA)

PDMA_DSCT4_CTL (DSCT4_CTL)

PDMA_CHCTL (CHCTL)

PDMA_STOP (STOP)

PDMA_SWREQ (SWREQ)

PDMA_TRGSTS (TRGSTS)

PDMA_PRISET (PRISET)

PDMA_PRICLR (PRICLR)

PDMA_INTEN (INTEN)

PDMA_INTSTS (INTSTS)

PDMA_ABTSTS (ABTSTS)

PDMA_TDSTS (TDSTS)

PDMA_SCATSTS (SCATSTS)

PDMA_TACTSTS (TACTSTS)

PDMA_SCATBA (SCATBA)

PDMA_DSCT4_ENDSA (DSCT4_ENDSA)

PDMA_DSCT4_ENDDA (DSCT4_ENDDA)

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA_REQSEL4_7 (REQSEL4_7)

PDMA_REQSEL8_11 (REQSEL8_11)

PDMA_REQSEL12_15 (REQSEL12_15)

PDMA_DSCT4_NEXT (DSCT4_NEXT)

PDMA_DSCT5_CTL (DSCT5_CTL)

PDMA_DSCT5_ENDSA (DSCT5_ENDSA)

PDMA_DSCT5_ENDDA (DSCT5_ENDDA)

PDMA_DSCT5_NEXT (DSCT5_NEXT)

PDMA_DSCT6_CTL (DSCT6_CTL)

PDMA_DSCT6_ENDSA (DSCT6_ENDSA)

PDMA_DSCT6_ENDDA (DSCT6_ENDDA)

PDMA_DSCT6_NEXT (DSCT6_NEXT)

PDMA_DSCT7_CTL (DSCT7_CTL)

PDMA_DSCT7_ENDSA (DSCT7_ENDSA)

PDMA_DSCT7_ENDDA (DSCT7_ENDDA)

PDMA_DSCT7_NEXT (DSCT7_NEXT)

PDMA_DSCT0_ENDDA (DSCT0_ENDDA)

PDMA_DSCT8_CTL (DSCT8_CTL)

PDMA_DSCT8_ENDSA (DSCT8_ENDSA)

PDMA_DSCT8_ENDDA (DSCT8_ENDDA)

PDMA_DSCT8_NEXT (DSCT8_NEXT)

PDMA_DSCT9_CTL (DSCT9_CTL)

PDMA_DSCT9_ENDSA (DSCT9_ENDSA)

PDMA_DSCT9_ENDDA (DSCT9_ENDDA)

PDMA_DSCT9_NEXT (DSCT9_NEXT)

PDMA_DSCT10_CTL (DSCT10_CTL)

PDMA_DSCT10_ENDSA (DSCT10_ENDSA)

PDMA_DSCT10_ENDDA (DSCT10_ENDDA)

PDMA_DSCT10_NEXT (DSCT10_NEXT)

PDMA_DSCT11_CTL (DSCT11_CTL)

PDMA_DSCT11_ENDSA (DSCT11_ENDSA)

PDMA_DSCT11_ENDDA (DSCT11_ENDDA)

PDMA_DSCT11_NEXT (DSCT11_NEXT)

PDMA_DSCT0_NEXT (DSCT0_NEXT)

PDMA_DSCT12_CTL (DSCT12_CTL)

PDMA_DSCT12_ENDSA (DSCT12_ENDSA)

PDMA_DSCT12_ENDDA (DSCT12_ENDDA)

PDMA_DSCT12_NEXT (DSCT12_NEXT)

PDMA_DSCT13_CTL (DSCT13_CTL)

PDMA_DSCT13_ENDSA (DSCT13_ENDSA)

PDMA_DSCT13_ENDDA (DSCT13_ENDDA)

PDMA_DSCT13_NEXT (DSCT13_NEXT)

PDMA_DSCT14_CTL (DSCT14_CTL)

PDMA_DSCT14_ENDSA (DSCT14_ENDSA)

PDMA_DSCT14_ENDDA (DSCT14_ENDDA)

PDMA_DSCT14_NEXT (DSCT14_NEXT)

PDMA_DSCT15_CTL (DSCT15_CTL)

PDMA_DSCT15_ENDSA (DSCT15_ENDSA)

PDMA_DSCT15_ENDDA (DSCT15_ENDDA)

PDMA_DSCT15_NEXT (DSCT15_NEXT)


PDMA_DSCT0_CTL (DSCT0_CTL)

Descriptor Table Control Register of PDMA Channel 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_CTL PDMA_DSCT0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE TXTYPE BURSIZE TBINTDIS SAINC DAINC TXWIDTH TXCNT

OPMODE : PDMA Operation Mode Selection\nNote: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

Stop Mode. Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically

#01 : 1

Basic Mode. The descriptor table only has one task. When this task is finished, the PDMA_INTSTS[x] will be asserted

#10 : 2

Scatter-Gather Mode. When operating in this mode, user must give the next descriptor table address in DSCTx_NEXT register PDMA will ignore this task, and then load the next task to execute

End of enumeration elements list.

TXTYPE : Request Type\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Burst request type

#1 : 1

Single request type

End of enumeration elements list.

BURSIZE : Burst Size\nThis field is used for peripheral to determine the burst size or used for determine the re-arbitration size. But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

128 transfers

#001 : 1

64 transfers

#010 : 2

32 transfers

#011 : 3

16 transfers

#100 : 4

8 transfers

#101 : 5

4 transfers

#110 : 6

2 transfers

#111 : 7

1 transfers

End of enumeration elements list.

TBINTDIS : Table Interrupt Disable Bit This field can be used to decide whether to enable table interrupt or not. When with transfer done flag, this bit is only used for scatter-gather mode. If the TBINTDIS bit is enabled when PDMA finishes this task, there will no interrupt generated. However, with the table empty flag, this bit is also useful. If it is set to '1 , the TEMPTYF will not be set when this situation has happened.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Table interrupt Enabled

#1 : 1

Table interrupt Disabled

End of enumeration elements list.

SAINC : Source Address Increment\nThis field is used to set the source address increment size\n
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#11 : 3

No Increment (Fixed Address.)

End of enumeration elements list.

DAINC : Destination Address Increment\nThis field is used to set the destination address increment size\n
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#11 : 3

No Increment (Fixed Address.)

End of enumeration elements list.

TXWIDTH : Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (DSCTx_ENDSA) and PDMA transfer destination address (DSCTx_ENDDA) should be alignment under the TXWIDTH selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

8 bits for every transfer item

#01 : 1

16 bits for every transfer item

#10 : 2

32 bits for every transfer item

#11 : 3

Reserved

End of enumeration elements list.

TXCNT : Transfer Count The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1) The maximum transfer count is 16384, every transfer may be byte, half-word or word that is dependent on TXWIDTH field. Note: When PDMA finish each transfer item, this field will be decrease imminently
bits : 16 - 29 (14 bit)
access : read-write


PDMA_DSCT1_CTL (DSCT1_CTL)

Descriptor Table Control Register of PDMA Channel 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_CTL PDMA_DSCT1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT0 (CURSCAT0)

Current Scatter-gather Descriptor Table Address of PDMA Channel 0
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT0 PDMA_CURSCAT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURADDR

CURADDR : PDMA External Current Descriptor Address Bits\nThis field indicates a 32-bit current external descriptor address of PDMA.\nNote: This field is read only and only used for Scatter-Gather mode to indicate the current external descriptor address.
bits : 0 - 31 (32 bit)
access : read-only


PDMA_CURSCAT1 (CURSCAT1)

Current Scatter-gather Descriptor Table Address of PDMA Channel 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT1 PDMA_CURSCAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT2 (CURSCAT2)

Current Scatter-gather Descriptor Table Address of PDMA Channel 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT2 PDMA_CURSCAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT3 (CURSCAT3)

Current Scatter-gather Descriptor Table Address of PDMA Channel 3
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT3 PDMA_CURSCAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT4 (CURSCAT4)

Current Scatter-gather Descriptor Table Address of PDMA Channel 4
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT4 PDMA_CURSCAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT5 (CURSCAT5)

Current Scatter-gather Descriptor Table Address of PDMA Channel 5
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT5 PDMA_CURSCAT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT6 (CURSCAT6)

Current Scatter-gather Descriptor Table Address of PDMA Channel 6
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT6 PDMA_CURSCAT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT7 (CURSCAT7)

Current Scatter-gather Descriptor Table Address of PDMA Channel 7
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT7 PDMA_CURSCAT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT8 (CURSCAT8)

Current Scatter-gather Descriptor Table Address of PDMA Channel 8
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT8 PDMA_CURSCAT8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT9 (CURSCAT9)

Current Scatter-gather Descriptor Table Address of PDMA Channel 9
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT9 PDMA_CURSCAT9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT10 (CURSCAT10)

Current Scatter-gather Descriptor Table Address of PDMA Channel 10
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT10 PDMA_CURSCAT10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT11 (CURSCAT11)

Current Scatter-gather Descriptor Table Address of PDMA Channel 11
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT11 PDMA_CURSCAT11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT12 (CURSCAT12)

Current Scatter-gather Descriptor Table Address of PDMA Channel 12
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT12 PDMA_CURSCAT12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT13 (CURSCAT13)

Current Scatter-gather Descriptor Table Address of PDMA Channel 13
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT13 PDMA_CURSCAT13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT14 (CURSCAT14)

Current Scatter-gather Descriptor Table Address of PDMA Channel 14
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT14 PDMA_CURSCAT14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CURSCAT15 (CURSCAT15)

Current Scatter-gather Descriptor Table Address of PDMA Channel 15
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CURSCAT15 PDMA_CURSCAT15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT1_ENDSA (DSCT1_ENDSA)

End Source Address Register of PDMA Channel 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_ENDSA PDMA_DSCT1_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT1_ENDDA (DSCT1_ENDDA)

End Destination Address Register of PDMA Channel 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_ENDDA PDMA_DSCT1_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT1_NEXT (DSCT1_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT1_NEXT PDMA_DSCT1_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_CTL (DSCT2_CTL)

Descriptor Table Control Register of PDMA Channel 2
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_CTL PDMA_DSCT2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_ENDSA (DSCT2_ENDSA)

End Source Address Register of PDMA Channel 2
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_ENDSA PDMA_DSCT2_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_ENDDA (DSCT2_ENDDA)

End Destination Address Register of PDMA Channel 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_ENDDA PDMA_DSCT2_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT2_NEXT (DSCT2_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT2_NEXT PDMA_DSCT2_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_CTL (DSCT3_CTL)

Descriptor Table Control Register of PDMA Channel 3
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_CTL PDMA_DSCT3_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_ENDSA (DSCT3_ENDSA)

End Source Address Register of PDMA Channel 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_ENDSA PDMA_DSCT3_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_ENDDA (DSCT3_ENDDA)

End Destination Address Register of PDMA Channel 3
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_ENDDA PDMA_DSCT3_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT3_NEXT (DSCT3_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT3_NEXT PDMA_DSCT3_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT0_ENDSA (DSCT0_ENDSA)

End Source Address Register of PDMA Channel 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_ENDSA PDMA_DSCT0_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDSA

ENDSA : PDMA Transfer Ending Source Address Bits\nThis field indicates a 32-bit ending source address of PDMA.\nNote: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.\n
bits : 0 - 31 (32 bit)
access : read-write


PDMA_DSCT4_CTL (DSCT4_CTL)

Descriptor Table Control Register of PDMA Channel 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_CTL PDMA_DSCT4_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_CHCTL (CHCTL)

PDMA Channel Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_CHCTL PDMA_CHCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHEN

CHEN : PDMA Channel Enable Control Bit[X]\nSet this bit to 1 to enable PDMA[x] operation. \nNote1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit.\nNote3: If each channel is not set as enabled, each channel cannot be active.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

PDMA channel [x] Disabled

1 : 1

PDMA channel [x] Enabled

End of enumeration elements list.


PDMA_STOP (STOP)

PDMA Stop Transfer Register
address_offset : 0x404 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_STOP PDMA_STOP write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP

STOP : PDMA Stop Transfer Bit [X] User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register. The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'. When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag. Software can poll channel enable bit to know if the on-going transfer is finished. Note1: This field is Write-Only Note2: Setting all PDMA_STOP bit to 1 will generate software reset to reset internal state machine (the embedded table will not be reset).
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

0 : 0

No effect

1 : 1

Stop PDMA transfer[x]

End of enumeration elements list.


PDMA_SWREQ (SWREQ)

PDMA Software Request Register
address_offset : 0x408 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_SWREQ PDMA_SWREQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWREQ

SWREQ : PDMA Software Request Bit [X]\nSet this bit to 1 to generate a software request to PDMA [x].\nNote1: This field is Write-Only. Software can indicate which channel is on active by reading PDMA_TRGSTS register. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable each PDMA channel, the software request will be ignored.
bits : 0 - 11 (12 bit)
access : write-only

Enumeration:

0 : 0

No effect

1 : 1

Generate a software request

End of enumeration elements list.


PDMA_TRGSTS (TRGSTS)

PDMA Request Active Flag Register
address_offset : 0x40C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_TRGSTS PDMA_TRGSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSTS

REQSTS : PDMA Request Active Flag [X]\nThis flag indicates whether channel[x] have a request or not.\nNote1: The request may come from software request (SWREQ) or peripheral request.\nNote2: When PDMA finishes channel transfer, this bit will be cleared automatically\nNote3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit.
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

0 : 0

Have no requests

1 : 1

Have a request

End of enumeration elements list.


PDMA_PRISET (PRISET)

PDMA Fixed Priority Setting Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_PRISET PDMA_PRISET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPRISET

FPRISET : PDMA Fixed Priority Setting Bit[X]\nSet this bit to 1 to enable fix priority level.\nThe PDMA channel priority is shown in the following table.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No effect

1 : 1

Set PDMA channel [x] be fixed priority channel

End of enumeration elements list.


PDMA_PRICLR (PRICLR)

PDMA Fixed Priority Clear Register
address_offset : 0x414 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_PRICLR PDMA_PRICLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPRICLR

FPRICLR : PDMA Fix Priority Clear Bit\nSet this bit to 1 to clear fixed priority level.\nNote: This field is Write-Only, and software can indicate the channel priority by reading PDMA_PRISET register.
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

0 : 0

No effect

1 : 1

Set PDMA channel [x] to be round-robin priority channel

End of enumeration elements list.


PDMA_INTEN (INTEN)

PDMA Interrupt Enable Control Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_INTEN PDMA_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTEN

INTEN : PDMA Interrupt Enable\nThis field is used for enabling PDMA channel[x] interrupt.\n
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

PDMA channel [x] interrupt Disabled

1 : 1

PDMA channel [x] interrupt Enabled

End of enumeration elements list.


PDMA_INTSTS (INTSTS)

PDMA Interrupt Status Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_INTSTS PDMA_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABTIF

ABTIF : PDMA Target Abort Status Flag This bit indicates which PDMA has target abort error Note: This field is read only, but software can write 1 to clear it.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No bus ERROR response received

1 : 1

Bus ERROR response received

End of enumeration elements list.


PDMA_ABTSTS (ABTSTS)

PDMA Read/Write Target Abort Flag Register
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_ABTSTS PDMA_ABTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_TDSTS (TDSTS)

PDMA Transfer Done Flag Register
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_TDSTS PDMA_TDSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TDIF

TDIF : Transfer Done Flag\nThis bit indicates which PDMA channel has finished transmission.\nNote: This field is read only, but software can write 1 to clear.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

Not finished yet

1 : 1

PDMA channel has finished transmission

End of enumeration elements list.


PDMA_SCATSTS (SCATSTS)

PDMA Scatter-gather Transfer Done Flag Register
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SCATSTS PDMA_SCATSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TEMPTYF

TEMPTYF : Table Empty Flag This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode Note: This field is read only, but software can write 1 to clear.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

Not finished or not in Stop mode

1 : 1

PDMA channel has finished transmission and the operation is Stop mode

End of enumeration elements list.


PDMA_TACTSTS (TACTSTS)

PDMA Transfer on Active Flag Register
address_offset : 0x42C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_TACTSTS PDMA_TACTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXACTF

TXACTF : Transfer On Active Flag\nThis bit indicates which PDMA channel is on active.\n
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

0 : 0

PDMA channel is not finished

1 : 1

PDMA channel is on active

End of enumeration elements list.


PDMA_SCATBA (SCATBA)

PDMA Scatter-gather Descriptor Table Base Address Register
address_offset : 0x43C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SCATBA PDMA_SCATBA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCATBA

SCATBA : PDMA Scatter-Gather Descriptor Table Base Address In Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is Note: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write


PDMA_DSCT4_ENDSA (DSCT4_ENDSA)

End Source Address Register of PDMA Channel 4
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_ENDSA PDMA_DSCT4_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT4_ENDDA (DSCT4_ENDDA)

End Destination Address Register of PDMA Channel 4
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_ENDDA PDMA_DSCT4_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA Source Module Select Register 0
address_offset : 0x480 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL0_3 PDMA_REQSEL0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC0 REQSRC1 REQSRC2 REQSRC3

REQSRC0 : Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 0. Software can configure the peripheral by setting REQSRC0.\n
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

#00000 : 0

Connect to SPI0_TX

#00001 : 1

Connect to SPI1_TX

#00010 : 2

Connect to SPI2_TX

#00011 : 3

Connect to SPI3_TX

#00100 : 4

Connect to UART0_TX

#00101 : 5

Connect to UART1_TX

#00110 : 6

Connect to UART2_TX

#00111 : 7

Connect to UART3_TX

#01000 : 8

Connect to UART4_TX

#01001 : 9

Connect to UART5_TX

#01010 : 10

Reserved

#01011 : 11

Connect to I2S_TX

#01100 : 12

Connect to I2S1_TX

#01101 : 13

Connect to SPI0_RX

#01110 : 14

Connect to SPI1_RX

#01111 : 15

Connect to SPI2_RX

#10000 : 16

Connect to SPI3_RX

#10001 : 17

Connect to UART0_RX

#10010 : 18

Connect to UART1_RX

#10011 : 19

Connect to UART2_RX

#10100 : 20

Connect to UART3_RX

#10101 : 21

Connect to UART4_RX

#10110 : 22

Connect to UART5_RX

#10111 : 23

Reserved

#11000 : 24

Connect to ADC

#11001 : 25

Connect to I2S_RX

#11010 : 26

Connect to I2S1_RX

End of enumeration elements list.

REQSRC1 : Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 1. Software can configure the peripheral setting by REQSRC1. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC2 : Channel 2 Selection \nThis filed defines which peripheral is connected to PDMA channel 2. Software can configure the peripheral setting by REQSRC2. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC3 : Channel 3 Selection \nThis filed defines which peripheral is connected to PDMA channel 3. Software can configure the peripheral setting by REQSRC3. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write


PDMA_REQSEL4_7 (REQSEL4_7)

PDMA Source Module Select Register 1
address_offset : 0x484 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL4_7 PDMA_REQSEL4_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC4 REQSRC5 REQSRC6 REQSRC7

REQSRC4 : Channel 0 Selection \nThis filed defines which peripheral is connected to PDMA channel 4. Software can configure the peripheral setting by REQSRC4. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write

REQSRC5 : Channel 1 Selection \nThis filed defines which peripheral is connected to PDMA channel 5. Software can configure the peripheral setting by REQSRC5. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC6 : Channel 6 Selection \nThis filed defines which peripheral is connected to PDMA channel 6. Software can configure the peripheral setting by REQSRC6. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC7 : Channel 7 Selection \nThis filed defines which peripheral is connected to PDMA channel 7. Software can configure the peripheral setting by REQSRC7. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write


PDMA_REQSEL8_11 (REQSEL8_11)

PDMA Source Module Select Register 2
address_offset : 0x488 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL8_11 PDMA_REQSEL8_11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC8 REQSRC9 REQSRC10 REQSRC11

REQSRC8 : Channel 8 Selection \nThis filed defines which peripheral is connected to PDMA channel 8. Software can configure the peripheral setting by REQSRC8. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write

REQSRC9 : Channel 9 Selection \nThis filed defines which peripheral is connected to PDMA channel 9. Software can configure the peripheral setting by REQSRC9. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC10 : Channel 10 Selection \nThis filed defines which peripheral is connected to PDMA channel 10. Software can configure the peripheral setting by REQSRC10. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC11 : Channel 11 Selection \nThis filed defines which peripheral is connected to PDMA channel 11. Software can configure the peripheral setting by REQSRC11. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write


PDMA_REQSEL12_15 (REQSEL12_15)

PDMA Source Module Select Register 3
address_offset : 0x48C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_REQSEL12_15 PDMA_REQSEL12_15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQSRC12 REQSRC13 REQSRC14 REQSRC15

REQSRC12 : Channel 12 Selection \nThis filed defines which peripheral is connected to PDMA channel 12. Software can configure the peripheral setting by REQSRC12. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write

REQSRC13 : Channel 13 Selection \nThis filed defines which peripheral is connected to PDMA channel 13. Software can configure the peripheral setting by REQSRC13. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC14 : Channel 14 Selection \nThis filed defines which peripheral is connected to PDMA channel 14. Software can configure the peripheral setting by REQSRC14. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC15 : Channel 15 Selection \nThis filed defines which peripheral is connected to PDMA channel 15. Software can configure the peripheral setting by REQSRC15. The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write


PDMA_DSCT4_NEXT (DSCT4_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 4
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT4_NEXT PDMA_DSCT4_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_CTL (DSCT5_CTL)

Descriptor Table Control Register of PDMA Channel 5
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_CTL PDMA_DSCT5_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_ENDSA (DSCT5_ENDSA)

End Source Address Register of PDMA Channel 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_ENDSA PDMA_DSCT5_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_ENDDA (DSCT5_ENDDA)

End Destination Address Register of PDMA Channel 5
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_ENDDA PDMA_DSCT5_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT5_NEXT (DSCT5_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 5
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT5_NEXT PDMA_DSCT5_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_CTL (DSCT6_CTL)

Descriptor Table Control Register of PDMA Channel 6
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_CTL PDMA_DSCT6_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_ENDSA (DSCT6_ENDSA)

End Source Address Register of PDMA Channel 6
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_ENDSA PDMA_DSCT6_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_ENDDA (DSCT6_ENDDA)

End Destination Address Register of PDMA Channel 6
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_ENDDA PDMA_DSCT6_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT6_NEXT (DSCT6_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 6
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT6_NEXT PDMA_DSCT6_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_CTL (DSCT7_CTL)

Descriptor Table Control Register of PDMA Channel 7
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_CTL PDMA_DSCT7_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_ENDSA (DSCT7_ENDSA)

End Source Address Register of PDMA Channel 7
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_ENDSA PDMA_DSCT7_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_ENDDA (DSCT7_ENDDA)

End Destination Address Register of PDMA Channel 7
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_ENDDA PDMA_DSCT7_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT7_NEXT (DSCT7_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 7
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT7_NEXT PDMA_DSCT7_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT0_ENDDA (DSCT0_ENDDA)

End Destination Address Register of PDMA Channel 0
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_ENDDA PDMA_DSCT0_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDDA

ENDDA : PDMA Transfer Ending Destination Address Bits\nThis field indicates a 32-bit ending destination address of PDMA.\nNote: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400.\n
bits : 0 - 31 (32 bit)
access : read-write


PDMA_DSCT8_CTL (DSCT8_CTL)

Descriptor Table Control Register of PDMA Channel 8
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_CTL PDMA_DSCT8_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT8_ENDSA (DSCT8_ENDSA)

End Source Address Register of PDMA Channel 8
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_ENDSA PDMA_DSCT8_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT8_ENDDA (DSCT8_ENDDA)

End Destination Address Register of PDMA Channel 8
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_ENDDA PDMA_DSCT8_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT8_NEXT (DSCT8_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 8
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT8_NEXT PDMA_DSCT8_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_CTL (DSCT9_CTL)

Descriptor Table Control Register of PDMA Channel 9
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_CTL PDMA_DSCT9_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_ENDSA (DSCT9_ENDSA)

End Source Address Register of PDMA Channel 9
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_ENDSA PDMA_DSCT9_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_ENDDA (DSCT9_ENDDA)

End Destination Address Register of PDMA Channel 9
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_ENDDA PDMA_DSCT9_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT9_NEXT (DSCT9_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 9
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT9_NEXT PDMA_DSCT9_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_CTL (DSCT10_CTL)

Descriptor Table Control Register of PDMA Channel 10
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_CTL PDMA_DSCT10_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_ENDSA (DSCT10_ENDSA)

End Source Address Register of PDMA Channel 10
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_ENDSA PDMA_DSCT10_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_ENDDA (DSCT10_ENDDA)

End Destination Address Register of PDMA Channel 10
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_ENDDA PDMA_DSCT10_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT10_NEXT (DSCT10_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 10
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT10_NEXT PDMA_DSCT10_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_CTL (DSCT11_CTL)

Descriptor Table Control Register of PDMA Channel 11
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_CTL PDMA_DSCT11_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_ENDSA (DSCT11_ENDSA)

End Source Address Register of PDMA Channel 11
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_ENDSA PDMA_DSCT11_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_ENDDA (DSCT11_ENDDA)

End Destination Address Register of PDMA Channel 11
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_ENDDA PDMA_DSCT11_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT11_NEXT (DSCT11_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 11
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT11_NEXT PDMA_DSCT11_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT0_NEXT (DSCT0_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 0
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT0_NEXT PDMA_DSCT0_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NEXT

NEXT : PDMA Next Description Table Offset Address Bits\nThis field indicates the offset of next descriptor table address in system memory.\nNote1: The next descriptor table address must be word boundary.\nNote2: The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100.\nNote3: Before filled transfer task in the description table, user must check if the descriptor table is complete.
bits : 2 - 15 (14 bit)
access : read-write


PDMA_DSCT12_CTL (DSCT12_CTL)

Descriptor Table Control Register of PDMA Channel 12
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT12_CTL PDMA_DSCT12_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT12_ENDSA (DSCT12_ENDSA)

End Source Address Register of PDMA Channel 12
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT12_ENDSA PDMA_DSCT12_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT12_ENDDA (DSCT12_ENDDA)

End Destination Address Register of PDMA Channel 12
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT12_ENDDA PDMA_DSCT12_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT12_NEXT (DSCT12_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 12
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT12_NEXT PDMA_DSCT12_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT13_CTL (DSCT13_CTL)

Descriptor Table Control Register of PDMA Channel 13
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT13_CTL PDMA_DSCT13_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT13_ENDSA (DSCT13_ENDSA)

End Source Address Register of PDMA Channel 13
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT13_ENDSA PDMA_DSCT13_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT13_ENDDA (DSCT13_ENDDA)

End Destination Address Register of PDMA Channel 13
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT13_ENDDA PDMA_DSCT13_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT13_NEXT (DSCT13_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 13
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT13_NEXT PDMA_DSCT13_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT14_CTL (DSCT14_CTL)

Descriptor Table Control Register of PDMA Channel 14
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT14_CTL PDMA_DSCT14_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT14_ENDSA (DSCT14_ENDSA)

End Source Address Register of PDMA Channel 14
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT14_ENDSA PDMA_DSCT14_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT14_ENDDA (DSCT14_ENDDA)

End Destination Address Register of PDMA Channel 14
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT14_ENDDA PDMA_DSCT14_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT14_NEXT (DSCT14_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 14
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT14_NEXT PDMA_DSCT14_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT15_CTL (DSCT15_CTL)

Descriptor Table Control Register of PDMA Channel 15
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT15_CTL PDMA_DSCT15_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT15_ENDSA (DSCT15_ENDSA)

End Source Address Register of PDMA Channel 15
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT15_ENDSA PDMA_DSCT15_ENDSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT15_ENDDA (DSCT15_ENDDA)

End Destination Address Register of PDMA Channel 15
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT15_ENDDA PDMA_DSCT15_ENDDA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDMA_DSCT15_NEXT (DSCT15_NEXT)

Scatter-gather Descriptor Table Offset Address of PDMA Channel 15
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_DSCT15_NEXT PDMA_DSCT15_NEXT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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