Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
PWM Clock Prescale Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC01 : PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC01 + 1). If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
bits : 0 - 7 (8 bit)
access : read-write
CLKPSC23 : PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC23 + 1). If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
bits : 8 - 15 (8 bit)
access : read-write
CLKPSC45 : PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM pair share one PWM counter base-clock prescaler. The base-clock of PWM counter is divided by (CLKPSC45 + 1). If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
bits : 16 - 23 (8 bit)
access : read-write
PWM Period Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register\nPERIOD determines the PWM period.\nNote1: Any write to PERIOD will take effect in next PWM cycle.\nNote2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE. If PERIOD equal to 0xFFFF, the PWM will work unpredictable.\nNote3: When PERIOD value is set to 0, PWM output is always high.
bits : 0 - 15 (16 bit)
access : read-write
PWM Period Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 4
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Period Register 5
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Compare Register\nCMP determines the PWM duty.\nNote: Any write to CMP will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
PWM Comparator Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 2
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 3
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 4
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Comparator Register 5
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Clock Divide Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV0 : PWM Counter Base-Clock Divide For PWMx_CH0\n (Table is the same as CLKDIV5)
bits : 0 - 2 (3 bit)
access : read-write
CLKDIV1 : PWM Counter Base-Clock Divide For PWMx_CH1\n (Table is the same as CLKDIV5)
bits : 4 - 6 (3 bit)
access : read-write
CLKDIV2 : PWM Counter Base-Clock Divide For PWMx_CH2\n (Table is the same as CLKDIV5)
bits : 8 - 10 (3 bit)
access : read-write
CLKDIV3 : PWM Counter Base-Clock Divide For PWMx_CH3\n (Table is the same as CLKDIV5)
bits : 12 - 14 (3 bit)
access : read-write
CLKDIV4 : PWM Counter Base-Clock Divide For PWMx_CH4\n (Table is the same as CLKDIV5)
bits : 16 - 18 (3 bit)
access : read-write
CLKDIV5 : PWM Counter Base-Clock Divide For PWMx_CH5\nThe base-clock of PWM counter is decided by clock pre-scalar and clock divider. Each PWM counter has independent clock divider control register and the divided value is listed in the table below:\n
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
2
#001 : 1
4
#010 : 2
8
#011 : 3
16
#100 : 4
1
End of enumeration elements list.
PWM Data Register 0
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : PWM Data Register\nUser can monitor CNT to know the current value in 16-bit down counter.\nNote: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
bits : 0 - 15 (16 bit)
access : read-only
PWM Data Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Data Register 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Mask Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN : PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWMn channel will be output with MSKDAT data. \nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM output signal is non-masked
1 : 1
PWM output signal is masked and output with MSKDAT data
End of enumeration elements list.
PWM Mask Data Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT : PWM Mask Data Bit:\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled.\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Output logic low to PWMn
1 : 1
Output logic high to PWMn
End of enumeration elements list.
PWM Dead-zone Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT01 : Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
bits : 0 - 7 (8 bit)
access : read-write
DTCNT23 : Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
bits : 8 - 15 (8 bit)
access : read-write
DTCNT45 : Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5\nThese 8-bit determine the Dead-zone length.\nThe unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
bits : 16 - 23 (8 bit)
access : read-write
DTDIV : Dead-Zone Generator Divider\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Dead-zone clock equal to PWM base clock divide 1
#01 : 1
Dead-zone clock equal to PWM base clock divide 2
#10 : 2
Dead-zone clock equal to PWM base clock divide 4
#11 : 3
Dead-zone clock equal to PWM base clock divide 8
End of enumeration elements list.
DTEN01 : Dead-Zone Enable Control for PWM Pair Of Channel 0 and Channel 1\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone insertion Disabled
#1 : 1
Dead-zone insertion Enabled
End of enumeration elements list.
DTEN23 : Dead-Zone Enable Control for PWM Pair Of Channel 2 and Channel 3\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone insertion Disabled
#1 : 1
Dead-zone insertion Enabled
End of enumeration elements list.
DTEN45 : Dead-Zone Enable Control for PWM Pair Of Channel 4 and Channel 5\nDead-zone insertion is only active when this pair of complementary PWM is enabled. If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-zone insertion Disabled
#1 : 1
Dead-zone insertion Enabled
End of enumeration elements list.
PWM Trigger Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTRGEN : PWM Period Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM period point trigger ADC function Disabled
1 : 1
PWM period point trigger ADC function Enabled
End of enumeration elements list.
CTRGEN : PWM Center Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM center point trigger ADC function Disabled
1 : 1
PWM center point trigger ADC function Enabled
End of enumeration elements list.
FTRGEN : PWM Falling Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM falling edge point trigger ADC function Disabled
1 : 1
PWM falling edge point trigger ADC function Enabled
End of enumeration elements list.
RTRGEN : PWM Rising Edge Point Trigger Enable Bits\nPWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.\nNote: Each bit controls the corresponding PWM channel.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM rising edge point trigger ADC function Disabled
1 : 1
PWM rising edge point trigger ADC function Enabled
End of enumeration elements list.
PWM Trigger ADC Status Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PTRGF : PWM Period Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
CTRGF : PWM Center Point Trigger Flag\nThis bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
FTRGF : PWM Falling Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
bits : 16 - 21 (6 bit)
access : read-write
RTRGF : PWM Rising Edge Point Trigger Indicator\nThis bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1. After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.\nNote1: Write 1 to clear this bit.\nNote2: Each bit controls the corresponding PWM channel.
bits : 24 - 29 (6 bit)
access : read-write
PWM Brake Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKP0EN : Brake0 Function Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake0 detect function Disabled
#1 : 1
Brake0 detect function Enabled
End of enumeration elements list.
BRK0NFDIS : PWM Brake 0 Noise Filter Disable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Enabled
#1 : 1
Noise filter of PWM Brake 0 Disabled
End of enumeration elements list.
BRK0INV : Inverse BKP0 State\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx0 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx0 is passed to the negative edge detector
End of enumeration elements list.
BRK0NFSEL : Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Filter clock = HCLK
#01 : 1
Filter clock = HCLK/2
#10 : 2
Filter clock = HCLK/4
#11 : 3
Filter clock = HCLK/16
End of enumeration elements list.
BRKP1EN : Brake1 Function Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake1 function Disabled
#1 : 1
Brake1 function Enabled
End of enumeration elements list.
BRK1NFDIS : PWM Brake 1 Noise Filter Disable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Enabled
#1 : 1
Noise filter of PWM Brake 1 Disabled
End of enumeration elements list.
BRK1INV : Inverse BKP1 State\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx1 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx1 is passed to the negative edge detector
End of enumeration elements list.
BK1SEL : Brake Function 1 Source Selection\n
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
From external pin BKP1
#01 : 1
From analog comparator 0 output (CPO0)
#10 : 2
From analog comparator 1 output (CPO1)
#11 : 3
Reserved
End of enumeration elements list.
BRK1NFSEL : Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
Filter clock = HCLK
#01 : 1
Filter clock = HCLK/2
#10 : 2
Filter clock = HCLK/4
#11 : 3
Filter clock = HCLK/16
End of enumeration elements list.
CPO0BKEN : CPO0 Digital Output As Brake0 Source Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO0 as one brake source in Brake 0 Disabled
#1 : 1
CPO0 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO1BKEN : CPO1 Digital Output As Brake 0 Source Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO1 as one brake source in Brake 0 Disabled
#1 : 1
CPO1 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO2BKEN : CPO2 Digital Output As Brake 0 Source Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO2 as one brake source in Brake 0 Disabled
#1 : 1
CPO2 as one brake source in Brake 0 Enabled
End of enumeration elements list.
LVDBKEN : Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function 1 triggered by Low-level detection Disabled
#1 : 1
Brake Function 1 triggered by Low-level detection Enabled
End of enumeration elements list.
BKOD : PWM Brake Output Data Register\nNote: Each bit controls the corresponding PWM channel.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM output low when fault brake conditions asserted
1 : 1
PWM output high when fault brake conditions asserted
End of enumeration elements list.
PWM Interrupt Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINTTYPE : PWM Period Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PIF[n] will be set if PWM counter underflow
1 : 1
PIF[n] will be set if PWM counter matches PWM_PERIODn register
End of enumeration elements list.
DINTTYPE : PWM Duty Interrupt Type Selection\nNote1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.\nNote2: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting
1 : 1
DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting
End of enumeration elements list.
PWM Interrupt Enable Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIEN : PWM Period Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Period interrupt Disabled
1 : 1
Period interrupt Enabled
End of enumeration elements list.
BRKIEN : Brake0 and Brak1 Interrupt Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flags BFK0 and BFK1 to trigger PWM interrupt
#1 : 1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
End of enumeration elements list.
DIEN : PWM Duty Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
Duty interrupt Disabled
1 : 1
Duty interrupt Enabled
End of enumeration elements list.
RLIEN : Rising Latch Interrupt Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
Rising latch interrupt Disabled
1 : 1
Rising latch interrupt Enabled
End of enumeration elements list.
FLIEN : Falling Latch Interrupt Enable Bit\nNote: Each bit controls the corresponding PWM channel.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
Falling latch interrupt Disabled
1 : 1
Falling latch interrupt Enabled
End of enumeration elements list.
PWM Interrupt Flag Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIF : PWM Period Interrupt Flag\nThis bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ). Software can write 1 to clear this bit to 0.
bits : 0 - 5 (6 bit)
access : read-write
BRKIF0 : PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#1 : 1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
End of enumeration elements list.
BRKIF1 : PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#1 : 1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
End of enumeration elements list.
DIF : PWM Duty Interrupt Flag\nFlag is set by hardware when channel 0 PWM counter down count and reaches CMP0. Software can clear this bit by writing 1 to it.\nNote: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
bits : 8 - 13 (6 bit)
access : read-write
BRKLK0 : PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 state is released
#1 : 1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
End of enumeration elements list.
CRLIF : Capture Rising Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
No capture rising latch condition happened
1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
BRKSTS0 : Brake 0 Status (Read Only)\n
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 0 state
#1 : 1
PWM is in Brake 0 state
End of enumeration elements list.
BRKSTS1 : Brake 1 Status (Read Only)\n
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 1 state
#1 : 1
PWM is in Brake 1 state
End of enumeration elements list.
CFLIF : Capture Falling Latch Interrupt Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
No capture falling latch condition happened
1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
PWM Output Enable Control Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN : PWM Pin Output Enable Bit\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM pin at tri-state
1 : 1
PWM pin in output mode
End of enumeration elements list.
PWM Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPINV : PWM Comparator Output Inverter Enable Bit\nWhen CMPINV is set to high, the PWM comparator output signals will be inversed, \nNote: Each bit control corresponding PWM channel
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Comparator output inverter Disabled
1 : 1
Comparator output inverter Enabled
End of enumeration elements list.
OUTMODE : PWM Output Mode\nThe register controls the output mode of PWM\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM output at independent mode
#1 : 1
PWM output at complementary mode
End of enumeration elements list.
GROUPEN : Group Mode Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of each PWM channel are independent
#1 : 1
Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0 and unify the signals timing of PWM_CH1, PWM_CH3 and PWM_CH5 in the same phase which is controlled by PWM_CH1
End of enumeration elements list.
PINV : PWM Output Polar Inverse Enable Bit\nThe register controls polarity state of PWM output\nNote: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM output polar inverse Disabled
1 : 1
PWM output polar inverse Enabled
End of enumeration elements list.
SYNCEN : Synchronous Mode Enable Bit\nNote: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of each PWM channel are independent
#1 : 1
Unify the signals timing of PWM_CH0 and PWM_CH1 in the same phase which is controlled by PWM0 and so as another two PWM pair
End of enumeration elements list.
CNTMODE : PWM Counter Operation Mode\nNote: Each bit control corresponding PWM channel\nNote: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM counter working as One-shot mode
1 : 1
PWM counter working as Auto-reload mode
End of enumeration elements list.
CNTTYPE : PWM Counter Operation Aligned Type\nNote: Each bit control corresponding PWM channel
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM counter operating as Edge-aligned type
1 : 1
PWM counter operating as Center-aligned type
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nNote: The PWM pin will keep output no matter ICE debug mode acknowledged or not.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects PWM output
#1 : 1
ICE debug mode acknowledgement disabled
End of enumeration elements list.
PWM Capture Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN : Capture Function Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture function Disabled. RCAPDAT and FCAPDAT will not be updated
1 : 1
Capture function Enabled. Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINV : Capture Inverter Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 8 - 13 (6 bit)
access : read-write
Enumeration:
0 : 0
Capture source inverter Disabled
1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN : Rising Latch Reload Enable Bits\n
bits : 16 - 21 (6 bit)
access : read-write
Enumeration:
0 : 0
Rising latch reload counter Enabled
1 : 1
Rising latch reload counter Enabled
End of enumeration elements list.
FCRLDEN : Falling Latch Reload Enable Bits\n
bits : 24 - 29 (6 bit)
access : read-write
Enumeration:
0 : 0
Falling latch reload counter Disabled
1 : 1
Falling latch reload counter Enabled
End of enumeration elements list.
PWM Capture Input Enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN : Capture Input Enable Bits\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0
1 : 1
PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
PWM Capture Status Register
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRIFOV : Rising Latch Interrupt Flag Overrun Status
This flag indicates if rising latch happened when the corresponding CRLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
bits : 0 - 5 (6 bit)
access : read-only
FLIFOV : Falling Latch Interrupt Flag Overrun Status
This flag indicates if falling latch happened when the corresponding CFLIF is 1
Note: This bit will be cleared automatically when user clear corresponding CFLIF.
bits : 8 - 13 (6 bit)
access : read-only
PWM Capture Rising Latch Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Falling Latch Register 0
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : Capture Falling Latch Register\nLatch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only
PWM Capture Rising Latch Register 1
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register 1
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register 2
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register 2
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register 3
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register 3
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register 4
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register 4
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Rising Latch Register 5
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Capture Falling Latch Register 5
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Counter Enable Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : PWM Counter Enable Bit\nNote: Each bit controls the corresponding PWM channel.
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM Counter Stop Running
1 : 1
PWM Counter Start Running
End of enumeration elements list.
PWM0 Synchronous Busy Status Register
address_offset : 0xE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (PWM_CTL[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (PWM_CTL[16]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM1 Synchronous Busy Status Register
address_offset : 0xE4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 counter operation mode CNTMOD (PWM_CTL [17]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD1/PWM_CMPDAT1/ PWM_CLKPSC or switch PWM1 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD1/PWM_CMPDAT1/PWM_CLKPSC or switch PWM1 operation mode CNTMOD (PWM_CTL [17]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM2 Synchronous Busy Status Register
address_offset : 0xE8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 counter operation mode CNTMOD (PWM_CTL [18]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD2/PWM_CMPDAT2/ PWM_CLKPSC or switch PWM2 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD2/PWM_CMPDAT2/PWM_CLKPSC or switch PWM2 operation mode CNTMOD (PWM_CTL [18]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM3 Synchronous Busy Status Register
address_offset : 0xEC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 counter operation mode CNTMOD (PWM_CTL [19]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD3/PWM_CMPDAT3/ PWM_CLKPSC or switch PWM3 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD3/PWM_CMPDAT3/PWM_CLKPSC or switch PWM3 operation mode CNTMOD (PWM_CTL [19]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM4 Synchronous Busy Status Register
address_offset : 0xF0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 counter operation mode CNTMOD (PWM_CTL [20]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD4/PWM_CMPDAT4/ PWM_CLKPSC or switch PWM4 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD4/PWM_CMPDAT4/PWM_CLKPSC or switch PWM4 operation mode CNTMOD (PWM_CTL [20]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
PWM5 Synchronous Busy Status Register
address_offset : 0xF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SYNCBUSY : PWM Synchronous Busy\nWhen software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 counter operation mode CNTMOD (PWM_CTL [21]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain. Software needs to check this busy status before writes PWM_PERIOD5/PWM_CMPDAT5/ PWM_CLKPSC or switch PWM5 counter operation mode to make sure previous setting has been update completely.\nThis bit will be set when software writes PWM_PERIOD5/PWM_CMPDAT5/PWM_CLKPSC or switch PWM5 operation mode CNTMOD (PWM_CTL [21]) and will be cleared by hardware automatically when PWM update these value completely.
bits : 0 - 0 (1 bit)
access : read-only
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