Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x48 byte (0x0)
mem_usage : registers
protection : not protected
PWM Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : PWM Mode Selection\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Independent mode
#01 : 1
Pair/Complementary mode
#10 : 2
Synchronized mode
#11 : 3
Reserved
End of enumeration elements list.
CLKDIV : PWM Clock Pre-Divider Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM clock = EPWM_CLK
#01 : 1
PWM clock = EPWM_CLK/2
#10 : 2
PWM clock = EPWM_CLK/4
#11 : 3
PWM clock = EPWM_CLK/16
End of enumeration elements list.
PWMIEN : PWM Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flag PIF to trigger PWM interrupt
#1 : 1
Enabling flag PIF can trigger PWM interrupt
End of enumeration elements list.
BRKIEN : Brake0 And Brak1 Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flags BRKIF0 and BRKIF1 to trigger PWM interrupt
#1 : 1
Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt
End of enumeration elements list.
LOAD : Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Compare Registers (EPWM_CMPDAT0~4) Control \nNote: This bit is software write, hardware clear and always read zero.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action if written with 0. The value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) are not loaded to PWM counter and Comparator registers
#1 : 1
Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM compare registers (EPWM_CMPDAT0~EPWM_CMPDAT4) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode
End of enumeration elements list.
CNTEN : Start CNTEN Control\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM stops running
#1 : 1
The PWM counter starts running
End of enumeration elements list.
INTTYPE : PWM Interrupt Type Selection\nNote: This bit is effective when PWM in central align mode only.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIF will be set if PWM counter underflow
#1 : 1
PIF will be set if PWM counter matches EPWM_PERIOD register
End of enumeration elements list.
PINV : Inverse PWM Comparator Output\nWhen PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse PWM comparator output
#1 : 1
Inverse PWM comparator output
End of enumeration elements list.
CNTCLR : Clear PWM Counter Control\nNote: It is automatically cleared by hardware.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#1 : 1
Clear 16-bit PWM counter to 000H
End of enumeration elements list.
CNTTYPE : PWM Aligned Type Selection\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Centre-aligned type
End of enumeration elements list.
GROUPEN : Group Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent
#1 : 1
Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0
End of enumeration elements list.
BRKP0INV : Inverse BKP0 State\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx0 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx0 is passed to the negative edge detector
End of enumeration elements list.
BRKP1INV : Inverse BKP1 State\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin BKPx1 is passed to the negative edge detector
#1 : 1
The inversed state of pin BKPx1 is passed to the negative edge detector
End of enumeration elements list.
BRKP0EN : BKPx0 Pin Trigger Brake Function0 Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx Brake Function 0 Disabled
#1 : 1
PWMx Brake Function 0 Enabled
End of enumeration elements list.
BRKP1EN : BKPx1 Pin Trigger Brake Function Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx Brake Function 1 Disabled
#1 : 1
PWMx Brake Function 1 Enabled
End of enumeration elements list.
BRK1SEL : Brake Function 1 Source Selection\n
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
From external pin BKPx1 (x=0~1 for unit0~1)
#01 : 1
From analog comparator 0 output (CPO0)
#10 : 2
From analog comparator 1 output (CPO1)
#11 : 3
From analog comparator 2 output (CPO2)
End of enumeration elements list.
BRK0NFSEL : Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Filter clock = HCLK
#01 : 1
Filter clock = HCLK/2
#10 : 2
Filter clock = HCLK/4
#11 : 3
Filter clock = HCLK/16
End of enumeration elements list.
BRK1NFSEL : Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Filter clock = HCLK
#01 : 1
Filter clock = HCLK/2
#10 : 2
Filter clock = HCLK/4
#11 : 3
Filter clock = HCLK/16
End of enumeration elements list.
CPO0BKEN : CPO0 Digital Output As Brake0 Source Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO0 as one brake source in Brake 0 Disabled
#1 : 1
CPO0 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO1BKEN : CPO1 Digital Output As Brake 0 Source Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO1 as one brake source in Brake 0 Disabled
#1 : 1
CPO1 as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO2BKEN : CPO2 Digital Output As Brake 0 Source Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
CPO2 as one brake source in Brake 0 Disabled
#1 : 1
CPO2 as one brake source in Brake 0 Enabled
End of enumeration elements list.
LVDBKEN : Low-Level Detection Trigger PWM Brake Function 1 Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function 1 triggered by Low-level detection Disabled
#1 : 1
Brake Function 1 triggered by Low-level detection Enabled
End of enumeration elements list.
BRK0NFDIS : PWM Brake 0 Noise Filter Disable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Enabled
#1 : 1
Noise filter of PWM Brake 0 Disabled
End of enumeration elements list.
BRK1NFDIS : PWM Brake 1 Noise Filter Disable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Enabled
#1 : 1
Noise filter of PWM Brake 1 Disabled
End of enumeration elements list.
CTRLD : Center Reload Mode Enable Bit\nThis bit only work when EPWM operation at center aligned mode.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM reload compare register at the period point of PWM counter
#1 : 1
EPWM reload compare register at the center point of PWM counter
End of enumeration elements list.
EPWM_CMPDAT2 Duty Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM_CMPDAT4 Duty Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Mask Mode Enable Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN : PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding EPWM_CHn channel will be output with EPWM_MSK[n] data. \n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM generator signal is output to next stage
1 : 1
PWM generator signal is masked and EPWM_MSK[n] is output to next stage
End of enumeration elements list.
PWM Mask Mode Data Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT : PWM Mask Data Bit\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Output logic low to EPWM_CHn
1 : 1
Output logic high to EPWM_CHn
End of enumeration elements list.
Asymmetric EPWM_CMPDAT0 Duty Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : Asymmetric PWM Duty Register\nWhen the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with EPWM_CMPDATx in the first half PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write
Asymmetric EPWM_CMPDAT2 Duty Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Asymmetric EPWM_CMPDAT4 Duty Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM Dead-time Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-Time Counter\nThe dead-time can be calculated from the following formula: \n
bits : 0 - 10 (11 bit)
access : read-write
DTEN0 : Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1)
End of enumeration elements list.
DTEN2 : Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3)
End of enumeration elements list.
DTEN4 : Dead-Time Insertion Enable Control for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5)
End of enumeration elements list.
PWM Brake Output
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKOUT : PWM Brake Output\nWhen PWM Brake is asserted, the PWM_CH0~5 output state before polarity control will follow bit0~5 setting, respectively.\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
The PWM_CHn output before polarity control is low when Brake is asserted
1 : 1
The PWM_CHn output before polarity control is high when Brake is asserted
End of enumeration elements list.
PWM Negative Polarity Control
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NEGPOLAR : PWM Negative Polarity Control\nThe register bit controls polarity/active state of real PWM output.\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM_CHn output is active high
1 : 1
PWM_CHn output is active low
End of enumeration elements list.
Asymmetric PWM Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASYMEN : Asymmetric PWM Enable Bit\nNote: This control bit is only valid when PWM module is set in Centre-aligned mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Asymmetric PWM function Disabled
#1 : 1
Asymmetric PWM function Enabled
End of enumeration elements list.
ASYMMODE0 : Asymmetric PWMx_CH0 Reload Mode Setting\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#01 : 1
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#10 : 2
1. PWM compare register 0 is reload CMP (EPWM_CMPDAT0[15:0]) at PWM cycle start
#11 : 3
Reserved
End of enumeration elements list.
ASYMMODE2 : Asymmetric PWMx_CH2 Reload Mode Setting\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#01 : 1
1. PWM compare register 2 is reload CMP (EPWM_CMPDAT2[15:0]) at PWM cycle start
#10 : 2
1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start
#11 : 3
Reserved
End of enumeration elements list.
ASYMMODE4 : Asymmetric PWMx_CH4 Reload Mode Setting\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#01 : 1
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#10 : 2
1. PWM compare register 4 is reload CMP (EPWM_CMPDAT4[15:0]) at PWM cycle start
#11 : 3
Reserved
End of enumeration elements list.
PIF Compared Counter
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIODCNT : PIF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt. \nPIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
bits : 0 - 3 (4 bit)
access : read-write
PWM Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKIF0 : PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one
#1 : 1
When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high
End of enumeration elements list.
BRKIF1 : PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one
#1 : 1
When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high
End of enumeration elements list.
PIF : PWM Period Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Counter has not up counted to the value of PERIOD or down counted with underflow
#1 : 1
Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode
End of enumeration elements list.
EIF0 : PWMx_CH0 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWMx_CH0 doesn't toggle
#1 : 1
Hardware will set this flag to high at the time of PWMx_CH0 rising or falling. If EDGEIEN0(EPWM_EINTCTL[8]) = 0, this bit is set when PWMx_CH0 falling is detected. If EDGEIEN0(EPWM_EINTCTL[8]) = 1, this bit is set when PWMx_CH0 rising is detected
End of enumeration elements list.
EIF2 : PWMx_CH2 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWMx_CH2 doesn't toggle
#1 : 1
Hardware will set this flag to high at the time of PWMx_CH2 rising or falling. If EDGEIEN2(EPWM_EINTCTL[9]) = 0, this bit is set when PWMx_CH2 falling is detected. If EDGEIEN2(EPWM_EINTCTL[9])= 1, this bit is set when PWMx_CH2 rising is detected
End of enumeration elements list.
EIF4 : PWMx_CH4 Edge Flag\nNote: This bit must be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWMx_CH4 doesn't toggle
#1 : 1
Hardware will set this flag to high at the time of PWMx_CH4 rising or falling. If EDGEIEN4(EPWM_EINTCTL[10]) = 0, this bit is set when PWMx_CH4 falling is detected. If EDGEIEN4(EPWM_EINTCTL[10]) = 1, this bit is set when PWMx_CH4 rising is detected
End of enumeration elements list.
BRK0LOCK : PWM Brake0 Locked \nNote: This bit must be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 state is released
#1 : 1
When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked
End of enumeration elements list.
BRK0STS : Brake 0 Status (Read Only)\n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 0 state
#1 : 1
PWM is in Brake 0 state
End of enumeration elements list.
BRK1STS : Brake 1 Status (Read Only)\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 1 state
#1 : 1
PWM is in Brake 1 state
End of enumeration elements list.
PWM Edge Interrupt Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGEIEN0 : PWMx0 Edge Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flag EIF0 to trigger PWM interrupt
#1 : 1
Enabling flag EIF0 can trigger PWM interrupt
End of enumeration elements list.
EDGEIEN2 : PWMx2 Edge Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabling flag EIF2 can trigger PWM interrupt
#1 : 1
Enabling flag EIF2 can trigger PWM interrupt
End of enumeration elements list.
EDGEIEN4 : PWMx4 Edge Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable flag EIF4 to trigger PWM interrupt
#1 : 1
Enabling flag EIF4 can trigger PWM interrupt
End of enumeration elements list.
EINTTYPE0 : PWMx0 Edge Interrupt Type\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EIF0 will be set if falling edge is detected at PWMx0
#1 : 1
EIF0 will be set if rising edge is detected at PWMx0
End of enumeration elements list.
EINTTYPE2 : PWMx2 Edge Interrupt Type\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EIF2 will be set if falling edge is detected at PWMx2
#1 : 1
EIF2 will be set if rising edge is detected at PWMx2
End of enumeration elements list.
EINTTYPE4 : PWMx4 Edge Interrupt Type\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EIF4 will be set if falling edge is detected at PWMx4
#1 : 1
EIF4 will be set if rising edge is detected at PWMx4
End of enumeration elements list.
PWM Output Enable Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENOUTEN : PWM Even Ports Output Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM even ports output Disabled (PWM even ports at tri-state)
#1 : 1
PWM even ports output Enabled
End of enumeration elements list.
ODDOUTEN : PWM Odd Ports Output Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM odd ports output Disabled (PWM even ports at tri-state)
#1 : 1
PWM odd ports output Enabled
End of enumeration elements list.
PWM Period Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : PWM Period Register\nEdge aligned:\n
bits : 0 - 15 (16 bit)
access : read-write
EPWM_CMPDAT0 Duty Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : PWM Duty Register\nEdge aligned:\n
bits : 0 - 15 (16 bit)
access : read-write
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