Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Input Capture Counter (24-bit Up Counter)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Input Capture Timer/Counter\nThe input Capture Timer/Counter is a 24-bit up-counting counter. The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Counter Compare Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Input Capture Counter Compare Register\n
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Control Register 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NFDIS : Noise Filter Clock Pre-Divide Selection\nTo determine the sampling frequency of the Noise Filter clock \n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP_CLK
#01 : 1
CAP_CLK/2
#10 : 2
CAP_CLK/4
#11 : 3
CAP_CLK/16
End of enumeration elements list.
CAPNF_DIS : Input Capture Noise Filter Disable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of Input Capture Enabled
#1 : 1
Noise filter of Input Capture Disabled
End of enumeration elements list.
CAPEN0 : Port Pin IC0 Input To Input Capture Unit Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC0 input to Input Capture Unit Disabled
#1 : 1
IC0 input to Input Capture Unit Enabled
End of enumeration elements list.
CAPEN1 : Port Pin IC1 Input To Input Capture Unit Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC1 input to Input Capture Unit Disabled
#1 : 1
IC1 input to Input Capture Unit Enabled
End of enumeration elements list.
CAPEN2 : Port Pin IC2 Input To Input Capture Unit Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
IC2 input to Input Capture Unit Disabled
#1 : 1
IC2 input to Input Capture Unit Enabled
End of enumeration elements list.
CAPSEL0 : CAP0 Input Source Selection\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP0 input is from port pin IC0
#01 : 1
CAP0 input is from signal CPO0 (Analog comparator 0 output)
#10 : 2
CAP0 input is from signal CHA of QEI controller unit x
#11 : 3
CAP0 input is from signal OPDO0 (OP0 digital output)
End of enumeration elements list.
CAPSEL1 : CAP1 Input Source Selection\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP1 input is from port pin IC1
#01 : 1
CAP1 input is from signal CPO1 (Analog comparator 1 output)
#10 : 2
CAP1 input is from signal CHB of QEI controller unit x
#11 : 3
CAP1 input is from signal OPDO1 (OP1 digital output)
End of enumeration elements list.
CAPSEL2 : CAP2 Input Source Selection\n
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP2 input is from port pin IC2
#01 : 1
CAP2 input is from signal CPO2 (Analog comparator 2 output)
#10 : 2
CAP2 input is from signal CHX of QEI controller unit x
#11 : 3
CAP2 input is from signal ADCMPOx (ADC compare output x)
End of enumeration elements list.
CAPIEN0 : Input Capture Channel 0 Interrupt Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPF0 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPF0 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CAPIEN1 : Input Capture Channel 1 Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPF1 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPF1 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CAPIEN2 : Input Capture Channel 2 Interrupt Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CAPF2 can trigger Input Capture interrupt Disabled
#1 : 1
The flag CAPF2 can trigger Input Capture interrupt Enabled
End of enumeration elements list.
OVIEN : OVF Trigger Input Capture Interrupt Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag OVUNF can trigger Input Capture interrupt Disabled
#1 : 1
The flag OVUNF can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CMPIEN : CMPF Trigger Input Capture Interrupt Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The flag CMPF can trigger Input Capture interrupt Disabled
#1 : 1
The flag CMPF can trigger Input Capture interrupt Enabled
End of enumeration elements list.
CNTEN : Input Capture Counter Start\nSetting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK). \n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP_CNT stop counting
#1 : 1
ECAP_CNT starts up-counting
End of enumeration elements list.
CMPCLR : Input Capture Counter Cleared By Compare-Match Control\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
CPTCLR : Input Capture Counter Cleared By Capture Events Control\nIf this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs. \n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled
#1 : 1
Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled
End of enumeration elements list.
RLDEN : Reload Function Enable Bit \nSetting this bit to enable the reload function. If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The reload function Disabled
#1 : 1
The reload function Enabled
End of enumeration elements list.
CMPEN : Compare Function Enable Bit\nThe compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set. \n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
The compare function Disabled
#1 : 1
The compare function Enabled
End of enumeration elements list.
CAPEN : Input Capture Timer/Counter Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input Capture function Disabled
#1 : 1
Input Capture function Enabled
End of enumeration elements list.
Input Capture Control Register 1
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDGESEL0 : Channel 0 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge
#01 : 1
Detect falling edge.\nDetect either rising or falling edge
End of enumeration elements list.
EDGESEL1 : Channel 1 Captured Edge Selection\nInput capture can detect falling edge change only, rising edge change only or one of both edge change \n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge
#01 : 1
Detect falling edge.\nDetect either rising or falling edge
End of enumeration elements list.
EDGESEL2 : Channel 2 Captured Edge Selection\nInput capture can detect falling edge change or rising edge change only, or one of both edge changes. \n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Detect rising edge
#01 : 1
Detect falling edge.\nDetect either rising or falling edge
End of enumeration elements list.
RLDSEL : ECAP_CNT Reload Trigger Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
CAPF0
#001 : 1
CAPF1
#010 : 2
CAPF2
#100 : 4
OVF
End of enumeration elements list.
CLKSEL : Capture Timer Clock Divide Selection\nThe capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[1:0].\n
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
CAP_CLK/1
#001 : 1
CAP_CLK/4
#010 : 2
CAP_CLK/16
#011 : 3
CAP_CLK/32
#100 : 4
CAP_CLK/64
#101 : 5
CAP_CLK/96
#110 : 6
CAP_CLK/112
#111 : 7
CAP_CLK/128
End of enumeration elements list.
SRCSEL : Capture Timer/Counter Clock Source Selection\nSelect the capture timer/counter clock source.\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
CAP_CLK (default)
#01 : 1
CAP0
#10 : 2
CAP1
#11 : 3
CAP2
End of enumeration elements list.
Input Capture Status Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPF0 : Input Capture Channel 0 Captured Flag\nWhen the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change is detected at CAP0 input
#1 : 1
A valid edge change is detected at CAP0 input
End of enumeration elements list.
CAPF1 : Input Capture Channel 1 Captured Flag\nWhen the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change is detected at CAP1 input
#1 : 1
A valid edge change is detected at CAP1 input
End of enumeration elements list.
CAPF2 : Input Capture Channel 2 Captured Flag\nWhen the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high. \nNote: This bit is only cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No valid edge change is detected at CAP2 input
#1 : 1
A valid edge change is detected at CAP2 input
End of enumeration elements list.
CMPF : Input Capture Compare-Match Flag\nIf the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.\nNote: This bit is only cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECAP_CNT does not match with ECAP_CNTCMP value
#1 : 1
ECAP_CNT counts to the same as ECAP_CNTCMP value
End of enumeration elements list.
OVF : Input Capture Counter Overflow Flag\nFlag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.\nNote: This bit is only cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow occurs in ECAP_CNT
#1 : 1
ECAP_CNT overflows
End of enumeration elements list.
Input Capture Counter Hold Register 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Input Capture Counter Hold Register\nWhen an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register. Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
bits : 0 - 23 (24 bit)
access : read-write
Input Capture Counter Hold Register 1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Input Capture Counter Hold Register 2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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