UART_DAT

UART_MODEM

UART_MODEMSTS

UART_FIFOSTS

UART_INTSTS

UART_TOUT

UART_BAUD

UART_IRDA

UART_ALTCTL

UART_FUNCSEL

UART_LINCTL

UART_LINSTS

UART_LINDEBUG

UART_INTEN

UART_SCCTL

UART_SCSTATUS

UART_FIFO

UART_LINE

DAT : Receiving/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The \nUART Controller will send out the data stored in transmitter FIFO top location through the \nUART_TXD. \nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO
bits : 0 - 7 (8 bit)
access : read-write

RTS : RTS (Request-To-Send) Signal \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSACTLV : RTS Trigger Level \nThis bit can change the RTS trigger level.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSSTS : RTS Pin State (Read Only) \nThis bit is the output pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only

CTSDETF : Detect CTS State Change Flag (Read Only) \nThis bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nSoftware can write 1 to clear this bit to 0
bits : 0 - 0 (1 bit)
access : read-only

CTSSTS : CTS Pin Status (Read Only) \nThis bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only

CTSACTLV : CTS Trigger Level \nThis bit can change the CTS trigger level.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVIF : RX Overflow Error IF (Read Only)\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.\nNote: This bit is read only, but it can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

SCERR : Smart Card Over Error Retry Flag\nIt is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))\nNote1: This field is used for SC function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDETF : RS-485 Address Byte Detection Flag (Read Only) \nNote1: This field is used for RS-485 function mode.\nNote2: This bit is read only, but it can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only

PEF : Parity Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but it can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only

FEF : Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but it can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-only

BIF : Break Interrupt Flag (Read Only) This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit. Note: This bit is read only, but it can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-only

RXPTR : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.
bits : 8 - 13 (6 bit)
access : read-only

RXEMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nWhen the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

RXFULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nThis bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

TXPTR : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
bits : 16 - 21 (6 bit)
access : read-only

TXEMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nWhen the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

TXFULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nThis bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

TXOVIF : TX Overflow Error Interrupt Flag (Read Only)\nIf TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. \nNote: This bit is read only, but it can be cleared by writing '1' to it.
bits : 24 - 24 (1 bit)
access : read-only

TXEMPTYF : Transmitter Empty Flag (Read Only)\nBit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nBit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

RDAIF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set. If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

RLSIF : Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: In SC function mode, this field includes error retry over flag . Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 2 - 2 (1 bit)
access : read-only

MODENIF : MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
bits : 3 - 3 (1 bit)
access : read-only

RXTOIF : Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

BUFERRIF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
bits : 5 - 5 (1 bit)
access : read-only

LINIF : LIN Bus Flag (Read Only)\nNote: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
bits : 7 - 7 (1 bit)
access : read-only

RDAINT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN and RDAIF are both set to 1.\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THREINT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN and THREIF are both set to 1.\n
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLSINT : Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN and RLSIF are both set to 1.\n
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEMINT : MODEM Status Interrupt Indicator (Read Only) \nThis bit is set if MODEMIEN and MODENIF are both set to 1.\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOINT : Time-Out Interrupt Indicator (Read Only)\nThis bit is set if TOCNTEN and RXTOIF are both set to 1.\n
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRINT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and BERRIF are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LININT : LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN and LINIF are both set to 1.\n
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWRLSIF : In DMA Mode, Receive Line Status Flag (Read Only) This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set). If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated. Note2: In SC function mode, this field includes error retry over flag . Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 18 - 18 (1 bit)
access : read-only

HWMODIF : In DMA Mode, MODEM Interrupt Flag (Read Only) \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
bits : 19 - 19 (1 bit)
access : read-only

HWTOIF : In DMA Mode, Time-Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If TOCNTEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated. \nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
bits : 20 - 20 (1 bit)
access : read-only

HWBUFEIF : In DMA Mode, Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set). When BERRIF is set, the transfer maybe is not correct. If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared when both TXOVIF and RXOVIF are cleared.
bits : 21 - 21 (1 bit)
access : read-only

HWRLSINT : In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN and HWRLSIF are both set to 1.\n
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWMODINT : In DMA Mode, MODEM Status Interrupt Indicator (Read Only) This bit is set if MODEMIEN and HWMODIF are both set to 1.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWTOINT : In DMA Mode, Time-Out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN and HWTOIF are both set to 1.\n
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HWBUFEINT : In DMA Mode, Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN and HWBFERIF are both set to 1.\n
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-Out Interrupt Comparator\n
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value \nThis field is use to programming the transfer delay time between the last stop bit and next start bit.\n\nNote: The counter clock is baud rate clock
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider\nThe field indicated the baud rate divider
bits : 0 - 15 (16 bit)
access : read-write

EDIVM1 : Divider X\n
bits : 24 - 27 (4 bit)
access : read-write

BAUDM0 : Divider X Equal To 1 Refer to the table below for more information.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BAUDM1 : Divider X Enable Bit\nRefer to the table below for more information.\nNote: In IrDA mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : IrDA Receiver/Transmitter Selection Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINV : IrDA Inverse Transmitting Output Signal\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINV : IrDA Inverse Receive Input Signal\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIXPULSE : Pulse width of TX is fixed 1.6us.
bits : 7 - 7 (1 bit)
access : read-write

LIN_BKFL : LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1.\n
bits : 0 - 3 (4 bit)
access : read-write

LINRXEN : LIN RX Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINTXEN : LIN TX Break Mode Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register. Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485NMM : RS-485 Normal Multi-Drop Operation Mode (NMM) \nNote: It can't be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AAD : RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It can't be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AUD : RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDEN : RS-485 Address Detection Enable Bit \nThis bit is use to enable RS-485 address detection mode. \nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMV : Address Match Value\nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUNCSEL : Function Select Enable Bit\n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVEN : LIN Slave Mode Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVHDEN : LIN Slave Header Detection Enable Bit\nNote2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVAREN : LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLVDUEN : LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).\nNote3: The control and interactions of this field are explained in 6.16.5.3.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTE : LIN Mute Mode Enable Bit\nNote: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.16.5.3.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SENDH : LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field depending on the setting HSEL register. Note: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDPEN : LIN ID Parity Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKDETEN : LIN Break Detection Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOFF : None
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITERREN : Bit Error Detect Enable Bit\nNote: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKFL : LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).\nNote2: This break field length is BRKFL + 1.\n
bits : 16 - 19 (4 bit)
access : read-write

BSL : LIN Break/Sync Delimiter Length\n\nNote: This bit used for LIN master to send header field.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSEL : LIN Header Selection\n
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PID : This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN] \n\nNote1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)\nNote2: This field can be used for LIN Master mode or Slave mode.
bits : 24 - 31 (8 bit)
access : read-write

SLVHDETF : LIN Slave Header Detection Flag (Read Only)\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLVHEF : LIN Slave Header Error Flag (Read Only) This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLVIDPEF : LIN Slave ID Parity Error Flag (Read Only)\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLVSYNCF : LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is read only, but can be cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.16.5.3.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKDETF : LIN Break Detection Flag (Read Only)\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\nNote1: This bit is read only, but can be cleared by writing 1 to it.\nNote2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BITEF : Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\nNote1: This bit is read only, but can be cleared by writing 1 to it.\n
bits : 9 - 9 (1 bit)
access : read-only

DEVERRF : LIN Header Deviation Error (Read Only)\nThis bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
bits : 0 - 0 (1 bit)
access : read-only

TOF : LIN Header Time-Out (Read Only)\nThis bit indicates the header error cause by the LIN header reception time-out.
bits : 1 - 1 (1 bit)
access : read-only

FRAMEERRF : LIN Header Frame Error Flag (Read Only)\nThis bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
bits : 2 - 2 (1 bit)
access : read-only

SYNCERRF : LIN Header Sync Data Error (Read Only)\nThis bit indicates the header error cause by the LIN received sync data is not 0x55.
bits : 3 - 3 (1 bit)
access : read-only

RDAIEN : Receive Data Available Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THREIEN : Transmit Holding Register Empty Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIEN : Receive Line Status Interrupt Enable Bit \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEMIEN : Modem Status Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIEN : RX Time-Out Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFERRIEN : Buffer Error Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKCTSIEN : UART Wake-Up Function Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINIEN : LIN RX Break Field Detected Interrupt Enable Bit\nNote: This field is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCNTEN : Time-Out Counter Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATORTSEN : RTS Auto Flow Control Enable Bit\nWhen RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATOCTSEN : CTS Auto Flow Control Enable Bit\nWhen CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXPDMAEN : TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPDMAEN : RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : RX Field Software Reset\nWhen RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will be automatically cleared for at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRST : TX Field Software Reset\nWhen TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear needs at least 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt (INT_RDA) Trigger Level\n
bits : 4 - 7 (4 bit)
access : read-write

RXOFF : Receiver Disable\nThe receiver is disabled or not.\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSTRGLV : RTS Trigger Level For Auto-Flow Control Use\n
bits : 16 - 19 (4 bit)
access : read-write

WLS : Word Length Selection\n
bits : 0 - 1 (2 bit)
access : read-write

NSB : Number Of STOP Bit Two STOP bit is generated when 6-, 7- and 8-bit word length is selected.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Bit\nThis bit is effective only when bit 3 (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control\nWhen this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write