PS2_CTL (CTL)

PS2_TXDAT3 (TXDAT3)

PS2_RXDAT (RXDAT)

PS2_STATUS (STATUS)

PS2_INTSTS (INTSTS)

PS2_TXDAT0 (TXDAT0)

PS2_TXDAT1 (TXDAT1)

PS2_TXDAT2 (TXDAT2)

PS2EN : PS/2 Device Enable Bit\nEnable PS/2 device controller.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXIEN : Transmit Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXIEN : Receive Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFDEPTH : Transmit Data FIFO Depth\nThere is 16-byte buffer for data transmit. Software can define the FIFO depth from 1 to 16 bytes depending on the application.\n
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACK : Acknowledge Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLRFIFO : Clear TX FIFO\nWrite 1 to this bit to terminate device to host transmission. The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not. The buffer content is not been cleared.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OVERRIDE : Software Override PS/2 CLK/DATA Pin State\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPS2CLK : Force CLKSTAT Line\nIt forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPS2DAT : Force DATSTAT Line\nIt forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAT : Received Data For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register. CPU must read this register before next byte reception complete otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1.
bits : 0 - 7 (8 bit)
access : read-only

CLKSTAT : CLK Pin State\nThis bit reflects the status of the CLKSTAT line after synchronizing.
bits : 0 - 0 (1 bit)
access : read-write

DATSTAT : DATA Pin State\nThis bit reflects the status of the DATSTAT line after synchronizing and sampling.
bits : 1 - 1 (1 bit)
access : read-write

FRAMEERR : Frame Error For host to device communication, if STOP bit (logic 1) is not received it is a frame error. If frame error occurs, DATA line may keep at low state after 12th clock. At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state. After that, device sends a Resend command to host. Note: Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXPARITY : Received Parity\nThis bit reflects the parity bit for the last received data byte (odd parity).\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-write

RXBUSY : Receive Busy\nThis bit indicates that the PS/2 device is currently receiving data.\nNote: This bit is read only.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXBUSY : Transmit Busy\nThis bit indicates that the PS/2 device is currently sending data.\nNote: This bit is read only.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOV : RX Buffer Overwrite\nNote: Write 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : TX FIFO Empty\nWhen software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled. When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.\nNote: This bit is read only.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BYTEIDX : Byte Index\n
bits : 8 - 11 (4 bit)
access : read-write

RXIF : Receive Interrupt\nThis bit is set to 1 when acknowledge bit is sent for Host to device communication. Interrupt occurs if RXIEN(PS2_CTL[2]) bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXIF : Transmit Interrupt\nThis bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit is set to 1.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAT : Transmit Data\nWrite data to this register starts device to host communication if bus is in IDLE state. Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
bits : 0 - 31 (32 bit)
access : read-write