I2C_CTL

I2C_CLKDIV

I2C_TOCTL

I2C_ADDR1

I2C_ADDR2

I2C_ADDR3

I2C_ADDRMSK0

I2C_ADDRMSK1

I2C_ADDRMSK2

I2C_ADDRMSK3

I2C_WKCTL

I2C_ADDR0

I2C_WKSTS

I2C_DAT

I2C_STATUS

AA : Assert Acknowledge Control\n
bits : 2 - 2 (1 bit)
access : read-write

SI : I2C Interrupt Flag\nWhen a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

STO : I2C STOP Control In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically. In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
bits : 4 - 4 (1 bit)
access : read-write

STA : I2C START Control\nSetting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
bits : 5 - 5 (1 bit)
access : read-write

I2CEN : I2C Controller Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : I2C Interrupt Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIVIDER : I2C Clock Divided Bits\nNote: The minimum value of DIVIDER is 4.
bits : 0 - 7 (8 bit)
access : read-write

TOIF : Time-Out Flag\nThis bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN (I2C_CTL[7])) is set to 1.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

TOCDIV4 : Time-Out Counter Input Clock Divided By 4\nWhen Enabled, The time-out period is extend 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOCEN : Time-Out Counter Enable Bit\nWhen Enabled, the 14-bit time-out counter will start counting when SI (I2C_CTL[3]) is clear. Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRMSK : I2C Address Mask Bits\nI2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care. If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : I2C Wake-Up Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GC : General Call Function\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR : I2C Address Bits\nThe content of this register is irrelevant when I2C is in Master mode. In the slave mode, the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write

WKIF : I2C Wake-Up Flag\nNote: Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DAT : I2C Data Bits\nBit [7:0] is located with the 8-bit transferred data of I2C serial port.
bits : 0 - 7 (8 bit)
access : read-write

STATUS : I2C Status Bits\nThe status register of I2C:\nThe three least significant bits are always 0. The five most significant bits contain the status code. Refer to section 6.19.5.4 for detail description.
bits : 0 - 7 (8 bit)
access : read-only