Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Transfer Control Enable Bit\nIn Master mode, the transfer will start when there is a data in the FIFO buffer after this is set to 1. In Slave mode, this device is ready to receive data when this bit is set to 1.\nNote: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer control Disabled
#1 : 1
Transfer control Enabled
End of enumeration elements list.
RXNEG : Receive On Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising edge of SPI bus clock
#1 : 1
Received data input signal is latched on the falling edge of SPI bus clock
End of enumeration elements list.
TXNEG : Transmit On Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising edge of SPI bus clock
#1 : 1
Transmitted data output signal is changed on the falling edge of SP bus clock
End of enumeration elements list.
CLKPOL : Clock Polarity\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI bus clock is idle low
#1 : 1
SPI bus clock is idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle\nExample:\n
bits : 4 - 7 (4 bit)
access : read-write
DWIDTH : Data Transmit Bit Width\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 8 - 12 (5 bit)
access : read-write
LSB : Send LSB First\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
End of enumeration elements list.
TWOBIT : 2-Bit Mode Enable Bit\nNote: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data. As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
2-bit mode Disabled
#1 : 1
2-bit mode Enabled
End of enumeration elements list.
UNITIEN : Unit Transfer Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit transfer interrupt Disabled
#1 : 1
SPI unit transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable Bit\nNote:\nByte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.\nByte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte Reorder function Disabled
#1 : 1
Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SUSPITV
End of enumeration elements list.
QDIODIR : Quad Or Dual I/O Mode Direction Control\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quad or Dual Input mode
#1 : 1
Quad or Dual Output mode
End of enumeration elements list.
DUALIOEN : Dual I/O Mode Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dual I/O mode Disabled
#1 : 1
Dual I/O mode Enabled
End of enumeration elements list.
QUADIOEN : Quad I/O Mode Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Quad I/O mode Disabled
#1 : 1
Quad I/O mode Enabled
End of enumeration elements list.
SPI FIFO Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Receive Reset\nNote: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
TXRST : Transmit Reset\nNote: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1. This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1. User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX FIFO threshold interrupt Disabled
#1 : 1
RX FIFO threshold interrupt Enabled
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX FIFO threshold interrupt Disabled
#1 : 1
TX FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTOIEN : Slave Receive Time-Out Interrupt Enable Bit (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive time-out interrupt Disabled
#1 : 1
Receive time-out interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overrun Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TXUFPOL : TX Underflow Data Polarity\nNote 1: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI data out is keep 0 if there is TX underflow event in Slave mode
#1 : 1
The SPI data out is keep 1 if there is TX underflow event in Slave mode
End of enumeration elements list.
TXUFIEN : TX Underflow Interrupt Enable Bit\nIn Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave TX underflow interrupt Disabled
#1 : 1
Slave TX underflow interrupt Enabled
End of enumeration elements list.
RXTH : Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write
TXTH : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write
SPI Status Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSY : Busy Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SPI controller is in idle state
#1 : 1
SPI controller is in busy state
End of enumeration elements list.
UNITIF : Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
SSACTIF : Slave Select Active Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt be cleared or not occurrs
#1 : 1
Slave select active interrupt event occurrs
End of enumeration elements list.
SSINAIF : Slave Select Inactive Interrupt Flag\nNote: Only available in Slave mode. This bit will be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt be cleared or not occurrs
#1 : 1
Slave select inactive interrupt event occurrs
End of enumeration elements list.
SSLINE : Slave Select Line Bus Status (Read Only)\nNote: This bit is only available in Slave mode. If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The slave select line status is 0
#1 : 1
The slave select line status is 1
End of enumeration elements list.
SLVTOIF : Slave Time-Out Interrupt Flag\nWhen the slave select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started. When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.\nNote: This bit will be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave time-out is not active
#1 : 1
Slave time-out is active
End of enumeration elements list.
SLVBEIF : Slave Mode Bit Count Error Interrupt Flag\nIn Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.\nNote: If the slave select active but there is no any bus clock input, the SLVBCEIF also be set when the slave select goes to inactive state. This bit will be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave mode bit count error event
#1 : 1
Slave mode bit count error event occurs
End of enumeration elements list.
SLVURIF : Slave Mode TX Under Run Interrupt Flag\nIn Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Slave TX under run event
#1 : 1
Slave TX under run event occurs
End of enumeration elements list.
RXEMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RXFULL : Receive FIFO Buffer Full Indicator (Read Only)\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Interrupt Flag (Read Only)\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RXTH
End of enumeration elements list.
RXOVIF : Receive FIFO Overrun Interrupt Flag\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO does not over run
#1 : 1
Receive FIFO over run
End of enumeration elements list.
RXTOIF : Receive Time-Out Interrupt Flag\nNote: This bit will be cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
SPIENSTS : SPI Enable Status (Read Only)\nNote: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
The SPI controller is disabled
#1 : 1
The SPI controller is enabled
End of enumeration elements list.
TXEMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Buffer Full Indicator (Read Only)\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Interrupt Flag (Read Only)\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH
End of enumeration elements list.
TXUFIF : TX Underflow Interrupt Flag\nWhen the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.\nNote 1: This bit will be cleared by writing 1 to it.\nNote 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 3 system clock cycles + 2 peripheral clock cycles since the reset operation is done.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
No data in Transmit FIFO and TX shift register when the slave selection signal is active
End of enumeration elements list.
TXRXRST : TX Or RX Reset Status (Read Only)\nNote: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
The reset function of TXRST or RXRST is done
#1 : 1
Doing the reset function of TXRST or RXRST
End of enumeration elements list.
RXCNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
SPI Data Transmit Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer. The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]) in SPI mode.\nFor example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: In Master mode, SPI controller will start to transfer after 1 APB clock cycle and 6 peripheral clock cycles after user writes to this register.
bits : 0 - 31 (32 bit)
access : write-only
SPI Data Receive Register
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThere are 8-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. This is a read only register.
bits : 0 - 31 (32 bit)
access : read-only
SPI Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation.
Note :
1. is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
2 .is the peripheral clock which is used to drive the SPI logic unit.
bits : 0 - 7 (8 bit)
access : read-write
SPI Slave Select Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Selection Control (Master Only)\nIf AUTOSS bit is cleared to 0,\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
set the SPIn_SS line to inactive state.\nKeep the SPIn_SS line at inactive state
#1 : 1
set the SPIn_SS line to active state.\nSPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2])
End of enumeration elements list.
SSACTPOL : Slave Selection Active Polarity\nThis bit defines the active polarity of slave selection signal (SPIn_SS).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave selection signal SPIn_SS is active low
#1 : 1
The slave selection signal SPIn_SS is active high
End of enumeration elements list.
AUTOSS : Automatic Slave Selection Function Enable Bit (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Automatic slave selection function Disabled. Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0])
#1 : 1
Automatic slave selection function Enabled
End of enumeration elements list.
SLV3WIRE : Slave 3-Wire Mode Enable Bit\nIn Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIn_CLK, SPIn_MISO and SPIn_MOSI pins.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-direction interface
#1 : 1
3-wire bi-direction interface
End of enumeration elements list.
SLVTOIEN : Slave Mode Time-Out Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode time-out interrupt Disabled
#1 : 1
Slave mode time-out interrupt Enabled
End of enumeration elements list.
SLVTORST : Slave Mode Time-Out Reset Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
When Slave mode time-out event occurs, the TX and RX control circuit will not be reset
#1 : 1
When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware
End of enumeration elements list.
SLVBEIEN : Slave Mode Bit Count Error Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode bit count error interrupt Disabled
#1 : 1
Slave mode bit count error interrupt Enabled
End of enumeration elements list.
SLVURIEN : Slave Mode TX Under Run Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave mode TX under run interrupt Disabled
#1 : 1
Slave mode TX under run interrupt Enabled
End of enumeration elements list.
SSACTIEN : Slave Select Active Interrupt Enable Bit \n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select active interrupt Disabled
#1 : 1
Slave select active interrupt Enabled
End of enumeration elements list.
SSINAIEN : Slave Select Inactive Interrupt Enable Bit \n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select inactive interrupt Disabled
#1 : 1
Slave select inactive interrupt Enabled
End of enumeration elements list.
SLVTOCNT : Slave Mode Time-Out Period \nIn Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active. The clock source of the time-out counter is Slave peripheral clock. If the value is 0, it indicates the slave mode time-out function is disabled.
bits : 16 - 31 (16 bit)
access : read-write
SPI PDMA Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : Transmit PDMA Enable Bit\nNote: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both functions simultaneously.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : Receive PDMA Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMARST : PDMA Reset\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0
End of enumeration elements list.
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