I2S_CTL (CTL)

I2S_TX (TX)

I2S_RX (RX)

I2S_CLKDIV (CLKDIV)

I2S_IEN (IEN)

I2S_STATUS (STATUS)

I2SEN : I2S Controller Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : Transmit Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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RXEN : Receive Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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MUTE : Transmit Mute Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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WDWIDTH : Word Width\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

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MONO : Monaural Data Control\nNote: when chip records data, only right channel data will be saved if monaural format is select.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

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FORMAT : Data Format Selection\n
bits : 7 - 7 (1 bit)
access : read-write

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SLAVE : Slave Mode Enable Bit\nNote: I2S can operate as master or slave. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro( NUC442/NUC472 series to Audio CODEC chip. In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
bits : 8 - 8 (1 bit)
access : read-write

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TXTH : Transmit FIFO Threshold Level\nNote: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHIF flag is set.
bits : 9 - 11 (3 bit)
access : read-write

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RXTH : Receive FIFO Threshold Level\nNote: When received data word(s) in buffer is equal to or higher than threshold level then RXTHIF flag is set.
bits : 12 - 14 (3 bit)
access : read-write

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MCLKEN : Master Clock Enable Bit Note: If the external crystal clock in NuMicro( NUC442/NUC472 series is frequency 2*N*256fs, software can program MCLKDIV(I2S_CLKDIV[5:0]) to get 256fs clock to audio codec chip.
bits : 15 - 15 (1 bit)
access : read-write

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RZCEN : Right Channel Zero-Cross Detection Enable Bit\nNote1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCIF(I2S_STATUS[22]) flag is set to 1.\nNote2: If RZCIF Flag is set to 1, the right channel will be mute.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

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LZCEN : Left Channel Zero-Cross Detect Enable Bit Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCIF(I2S_STATUS[23]) flag is set to 1. Note2: If LZCIF Flag is set to 1, the left channel will be mute.
bits : 17 - 17 (1 bit)
access : read-write

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TXCLR : Clear Transmit FIFO\nNote1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. \nNote2: This bit is clear by hardware automatically, read it return zero.
bits : 18 - 18 (1 bit)
access : read-write

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RXCLR : Clear Receive FIFO\nNote1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.\nNote2: This bit is cleared by hardware automatically, read it return zero.
bits : 19 - 19 (1 bit)
access : read-write

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TXPDMAEN : Transmit DMA Enable Bit\nNote: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
bits : 20 - 20 (1 bit)
access : read-write

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RXPDMAEN : Receive DMA Enable Bit\nNote: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
bits : 21 - 21 (1 bit)
access : read-write

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RXLCH : Receive Left Channel Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write

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PCMEN : PCM Interface Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX : Transmit FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data transmit. Write data to this register to prepare data for transmit. The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]).
bits : 0 - 31 (32 bit)
access : write-only

RX : Receive FIFO Bits\nI2S contains 8 words (8x32 bit) data buffer for data receive. Read this register to get data in FIFO. The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]).
bits : 0 - 31 (32 bit)
access : read-only

MCLKDIV : Master Clock Divider\nIf chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip. If MCLKDIV is set to 0, MCLK is the same as external clock input.\nNote: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK
bits : 0 - 5 (6 bit)
access : read-write

BCLKDIV : Bit Clock Divider\nIf I2S operates in Master mode, bit clock is provided by the NuMicro( NUC442/NUC472 series. Software can program these bits to generate sampling rate clock frequency.\nNote: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
bits : 8 - 16 (9 bit)
access : read-write

RXUDIEN : Receive FIFO Underflow Interrupt E Enable Bit\nNote: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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RXOVIEN : Receive FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and RXOVIF(I2S_STATUS[9]) flag is set to 1
bits : 1 - 1 (1 bit)
access : read-write

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RXTHIEN : Receive FIFO Threshold Level Interrupt Enable Bit\nNote: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHIF bit is set to 1. If RXTHIEN bit is enabled, interrupt occur.
bits : 2 - 2 (1 bit)
access : read-write

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TXUDIEN : Transmit FIFO Underflow Interrupt Enable Bit\nNote: Interrupt occur if this bit is set to 1 and TXUDIF(I2S_STATUS[16]) flag is set to 1.
bits : 8 - 8 (1 bit)
access : read-write

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TXOVIEN : Transmit FIFO Overflow Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and TXOVIF(I2S_STATUS[17]) flag is set to 1
bits : 9 - 9 (1 bit)
access : read-write

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TXTHIEN : Transmit FIFO Threshold Level Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]).
bits : 10 - 10 (1 bit)
access : read-write

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RZCIEN : Right Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and right channel zero-cross
bits : 11 - 11 (1 bit)
access : read-write

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LZCIEN : Left Channel Zero-Cross Interrupt Enable Bit\nNote: Interrupt occurs if this bit is set to 1 and left channel zero-cross
bits : 12 - 12 (1 bit)
access : read-write

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I2SIF : I2S Interrupt Flag (Read Only)\nNote: It is wire-OR of TXIF and RXIF bits.
bits : 0 - 0 (1 bit)
access : read-only

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RXIF : I2S Receive Interrupt (Read Only)\n
bits : 1 - 1 (1 bit)
access : read-only

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TXIF : I2S Transmit Interrupt (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only

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RIGHT : Right Channel (Read Only)\nNote: This bit indicate current transmit data is belong to right channel
bits : 3 - 3 (1 bit)
access : read-only

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RXUDIF : Receive FIFO Underflow Flag\nNote1: When receive FIFO is empty, and software reads the receive FIFO again. This bit will be set to 1, and it indicates underflow situation occurs.\nNote2: Write 1 to clear this bit to zero
bits : 8 - 8 (1 bit)
access : read-write

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RXOVIF : Receive FIFO Overflow Flag\nNote1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.\nNote2: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

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RXTHIF : Receive FIFO Threshold Flag (Read Only)\nNote: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1. It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register.
bits : 10 - 10 (1 bit)
access : read-only

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RXFULL : Receive FIFO Full (Read Only)\nNote: This bit reflects data words number in receive FIFO is 8.
bits : 11 - 11 (1 bit)
access : read-only

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RXEMPTY : Receive FIFO Empty (Read Only)\nNote: This bit reflects data words number in receive FIFO is zero
bits : 12 - 12 (1 bit)
access : read-only

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TXUDIF : Transmit FIFO Underflow Flag\nNote1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.\nNote2: Write 1 to clear this bit to 0.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVIF : Transmit FIFO Overflow Flag\nNote1: Write data to transmit FIFO when it is full and this bit set to 1\nNote2: Write 1 to clear this bit to 0.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIF : Transmit FIFO Threshold Flag (Read Only)\nNote: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1. It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register.
bits : 18 - 18 (1 bit)
access : read-only

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TXFULL : Transmit FIFO Full (Read Only)\nThis bit reflect data word number in transmit FIFO is 8\n
bits : 19 - 19 (1 bit)
access : read-only

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TXEMPTY : Transmit FIFO Empty (Read Only)\nThis bit reflect data word number in transmit FIFO is zero\n
bits : 20 - 20 (1 bit)
access : read-only

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TXBUSY : Transmit Busy (Read Only)\nNote: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out. And set to 1 when 1st data is load to shift buffer.
bits : 21 - 21 (1 bit)
access : read-only

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RZCIF : Right Channel Zero-Cross Flag\nIt indicates right channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
bits : 22 - 22 (1 bit)
access : read-write

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End of enumeration elements list.

LZCIF : Left Channel Zero-Cross Flag\nIt indicates left channel next sample data sign bit is changed or all data bits are zero.\nNote: Write 1 to clear this bit to 0.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

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RXCNT : Receive FIFO Level (Read Only)\nThese bits indicate word number in receive FIFO\n
bits : 24 - 27 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXCNT : Transmit FIFO Level (Read Only)\nThese bits indicate word number in transmit FIFO\n
bits : 28 - 31 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.