USBD

USBIEN : USB Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

CEPIEN : Control Endpoint Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPAIEN : Interrupt Enable Control for Endpoint A \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPBIEN : Interrupt Enable Control for Endpoint B \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B \n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPCIEN : Interrupt Enable Control for Endpoint C \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPDIEN : Interrupt Enable Control for Endpoint D \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D\n
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPEIEN : Interrupt Enable Control for Endpoint E \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E\n
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPFIEN : Interrupt Enable Control for Endpoint F \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F\n
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPGIEN : Interrupt Enable Control for Endpoint G\nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPHIEN : Interrupt Enable Control for Endpoint H \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H\n
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPIIEN : Interrupt Enable Control for Endpoint I \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I\n
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPJIEN : Interrupt Enable Control for Endpoint J \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPKIEN : Interrupt Enable Control for Endpoint K \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K\n
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

EPLIEN : Interrupt Enable Control for Endpoint L \nWhen set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

#0 : 0

The related interrupt Disabled

#1 : 1

The related interrupt Enabled

End of enumeration elements list.

USBD_BUSINTSTS (BUSINTSTS)

USB Bus Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOFIF : SOF Receive Control\nThis bit indicates when a start-of-frame packet has been received. \nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No start-of-frame packet has been received

#1 : 1

Start-of-frame packet has been received

End of enumeration elements list.

RSTIF : Reset Status \nWhen set, this bit indicates that either the USB root port reset is end.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No USB root port reset is end

#1 : 1

USB root port reset is end

End of enumeration elements list.

RESUMEIF : Resume \nWhen set, this bit indicates that a device resume has occurred.\nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No device resume has occurred

#1 : 1

Device resume has occurred

End of enumeration elements list.

SUSPENDIF : Suspend Request \nThis bit is set as default and it has to be cleared by writing '1' before the USB reset. This bit is also set when a USB Suspend request is detected from the host. \nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No USB Suspend request is detected from the host

#1 : 1

USB Suspend request is detected from the host

End of enumeration elements list.

HISPDIF : High-Speed Settle \nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No valid high-speed reset protocol is detected

#1 : 1

Valid high-speed reset protocol is over and the device has settled in high-speed

End of enumeration elements list.

DMADONEIF : DMA Completion Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No DMA transfer over

#1 : 1

DMA transfer is over

End of enumeration elements list.

PHYCLKVLDIF : Usable Clock Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Usable clock is not available

#1 : 1

Usable clock is available from the transceiver

End of enumeration elements list.

VBUSDETIF : VBUS Detection Interrupt Status \nNote: Write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No VBUS is plug-in

#1 : 1

VBUS is plug-in

End of enumeration elements list.

USBD_EPDBUFEND (EPDBUFEND)

Endpoint D RAM End Address Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEDAT (EPEDAT)

Endpoint E Data Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEINTSTS (EPEINTSTS)

Endpoint E Interrupt Status Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEINTEN (EPEINTEN)

Endpoint E Interrupt Enable Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEDATCNT (EPEDATCNT)

Endpoint E Data Available Count Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPERSPCTL (EPERSPCTL)

Endpoint E Response Control Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEMPS (EPEMPS)

Endpoint E Maximum Packet Size Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPETXCNT (EPETXCNT)

Endpoint E Transfer Count Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPECFG (EPECFG)

Endpoint E Configuration Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEBUFSTART (EPEBUFSTART)

Endpoint E RAM Start Address Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPEBUFEND (EPEBUFEND)

Endpoint E RAM End Address Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFDAT (EPFDAT)

Endpoint F Data Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFINTSTS (EPFINTSTS)

Endpoint F Interrupt Status Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFINTEN (EPFINTEN)

Endpoint F Interrupt Enable Register
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFDATCNT (EPFDATCNT)

Endpoint F Data Available Count Register
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFRSPCTL (EPFRSPCTL)

Endpoint F Response Control Register
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_BUSINTEN (BUSINTEN)

USB Bus Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOFIEN : SOF Interrupt\nThis bit enables the SOF interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

SOF interrupt Disabled

#1 : 1

SOF interrupt Enabled

End of enumeration elements list.

RSTIEN : Reset Status \nThis bit enables the USB-Reset interrupt.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

USB-Reset interrupt Disabled

#1 : 1

USB-Reset interrupt Enabled

End of enumeration elements list.

RESUMEIEN : Resume \nThis bit enables the Resume interrupt.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Resume interrupt Disabled

#1 : 1

Resume interrupt Enabled

End of enumeration elements list.

SUSPENDIEN : Suspend Request \nThis bit enables the Suspend interrupt.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Suspend interrupt Disabled

#1 : 1

Suspend interrupt Enabled

End of enumeration elements list.

HISPDIEN : High-Speed Settle \nThis bit enables the high-speed settle interrupt.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

High-speed settle interrupt Disabled

#1 : 1

High-speed settle interrupt Enabled

End of enumeration elements list.

DMADONEIEN : DMA Completion Interrupt \nThis bit enables the DMA completion interrupt\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA completion interrupt Disabled

#1 : 1

DMA completion interrupt Enabled

End of enumeration elements list.

PHYCLKVLDIEN : Usable Clock Interrupt\nThis bit enables the usable clock interrupt.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Usable clock interrupt Disabled

#1 : 1

Usable clock interrupt Enabled

End of enumeration elements list.

VBUSDETIEN : VBUS Detection Interrupt Enable Bit\nThis bit enables the VBUS floating detection interrupt.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

VBUS floating detection interrupt Disabled

#1 : 1

VBUS floating detection interrupt Enabled

End of enumeration elements list.

USBD_EPFMPS (EPFMPS)

Endpoint F Maximum Packet Size Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFTXCNT (EPFTXCNT)

Endpoint F Transfer Count Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFCFG (EPFCFG)

Endpoint F Configuration Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFBUFSTART (EPFBUFSTART)

Endpoint F RAM Start Address Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPFBUFEND (EPFBUFEND)

Endpoint F RAM End Address Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGDAT (EPGDAT)

Endpoint G Data Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGINTSTS (EPGINTSTS)

Endpoint G Interrupt Status Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGINTEN (EPGINTEN)

Endpoint G Interrupt Enable Register
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGDATCNT (EPGDATCNT)

Endpoint G Data Available Count Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGRSPCTL (EPGRSPCTL)

Endpoint G Response Control Register
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGMPS (EPGMPS)

Endpoint G Maximum Packet Size Register
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGTXCNT (EPGTXCNT)

Endpoint G Transfer Count Register
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGCFG (EPGCFG)

Endpoint G Configuration Register
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGBUFSTART (EPGBUFSTART)

Endpoint G RAM Start Address Register
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPGBUFEND (EPGBUFEND)

Endpoint G RAM End Address Register
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHDAT (EPHDAT)

Endpoint H Data Register
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_OPER (OPER)

USB Operational Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESUMEEN : Generate Resume\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Resume sequence to be initiated to the host

#1 : 1

A Resume sequence to be initiated to the host if device remote wakeup is enabled. This bit is self-clearing

End of enumeration elements list.

HISPDEN : USB High-Speed\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host

#1 : 1

The USB device controller to initiate a chirp-sequence during reset protocol

End of enumeration elements list.

CURSPD : USB Current Speed\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The device has settled in Full Speed

#1 : 1

The USB device controller has settled in High-speed

End of enumeration elements list.

USBD_EPHINTSTS (EPHINTSTS)

Endpoint H Interrupt Status Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHINTEN (EPHINTEN)

Endpoint H Interrupt Enable Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHDATCNT (EPHDATCNT)

Endpoint H Data Available Count Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHRSPCTL (EPHRSPCTL)

Endpoint H Response Control Register
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHMPS (EPHMPS)

Endpoint H Maximum Packet Size Register
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHTXCNT (EPHTXCNT)

Endpoint H Transfer Count Register
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHCFG (EPHCFG)

Endpoint H Configuration Register
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHBUFSTART (EPHBUFSTART)

Endpoint H RAM Start Address Register
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPHBUFEND (EPHBUFEND)

Endpoint H RAM End Address Register
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIDAT (EPIDAT)

Endpoint I Data Register
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIINTSTS (EPIINTSTS)

Endpoint I Interrupt Status Register
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIINTEN (EPIINTEN)

Endpoint I Interrupt Enable Register
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIDATCNT (EPIDATCNT)

Endpoint I Data Available Count Register
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIRSPCTL (EPIRSPCTL)

Endpoint I Response Control Register
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIMPS (EPIMPS)

Endpoint I Maximum Packet Size Register
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPITXCNT (EPITXCNT)

Endpoint I Transfer Count Register
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_FRAMECNT (FRAMECNT)

USB Frame Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MFRAMECNT : Micro-Frame Counter\nThis field contains the micro-frame number for the frame number in the frame counter field.
bits : 0 - 2 (3 bit)
access : read-only

FRAMECNT : Frame Counter\nThis field contains the frame count from the most recent start-of-frame packet.
bits : 3 - 13 (11 bit)
access : read-only

USBD_EPICFG (EPICFG)

Endpoint I Configuration Register
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIBUFSTART (EPIBUFSTART)

Endpoint I RAM Start Address Register
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPIBUFEND (EPIBUFEND)

Endpoint I RAM End Address Register
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJDAT (EPJDAT)

Endpoint J Data Register
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJINTSTS (EPJINTSTS)

Endpoint J Interrupt Status Register
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJINTEN (EPJINTEN)

Endpoint J Interrupt Enable Register
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJDATCNT (EPJDATCNT)

Endpoint J Data Available Count Register
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJRSPCTL (EPJRSPCTL)

Endpoint J Response Control Register
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJMPS (EPJMPS)

Endpoint J Maximum Packet Size Register
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJTXCNT (EPJTXCNT)

Endpoint J Transfer Count Register
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJCFG (EPJCFG)

Endpoint J Configuration Register
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJBUFSTART (EPJBUFSTART)

Endpoint J RAM Start Address Register
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPJBUFEND (EPJBUFEND)

Endpoint J RAM End Address Register
address_offset : 0x1F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKDAT (EPKDAT)

Endpoint K Data Register
address_offset : 0x1F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKINTSTS (EPKINTSTS)

Endpoint K Interrupt Status Register
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKINTEN (EPKINTEN)

Endpoint K Interrupt Enable Register
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_FADDR (FADDR)

USB Function Address Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADDR : USB Function Address\nThis field contains the current USB address of the device. This field is cleared when a root port reset is detected.
bits : 0 - 6 (7 bit)
access : read-write

USBD_EPKDATCNT (EPKDATCNT)

Endpoint K Data Available Count Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKRSPCTL (EPKRSPCTL)

Endpoint K Response Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKMPS (EPKMPS)

Endpoint K Maximum Packet Size Register
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKTXCNT (EPKTXCNT)

Endpoint K Transfer Count Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKCFG (EPKCFG)

Endpoint K Configuration Register
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKBUFSTART (EPKBUFSTART)

Endpoint K RAM Start Address Register
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPKBUFEND (EPKBUFEND)

Endpoint K RAM End Address Register
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLDAT (EPLDAT)

Endpoint L Data Register
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLINTSTS (EPLINTSTS)

Endpoint L Interrupt Status Register
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLINTEN (EPLINTEN)

Endpoint L Interrupt Enable Register
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLDATCNT (EPLDATCNT)

Endpoint L Data Available Count Register
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLRSPCTL (EPLRSPCTL)

Endpoint L Response Control Register
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLMPS (EPLMPS)

Endpoint L Maximum Packet Size Register
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLTXCNT (EPLTXCNT)

Endpoint L Transfer Count Register
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLCFG (EPLCFG)

Endpoint L Configuration Register
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPLBUFSTART (EPLBUFSTART)

Endpoint L RAM Start Address Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_TEST (TEST)

USB Test Mode Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TESTMODE : Test Mode Selection\nNote: This field is cleared when root port reset is detected.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Normal Operation

#001 : 1

Test_J

#010 : 2

Test_K

#011 : 3

Test_SE0_NAK

#100 : 4

Test_Packet

#101 : 5

Test_Force_Enable

#110 : 6

Reserved

#111 : 7

Reserved

End of enumeration elements list.

USBD_EPLBUFEND (EPLBUFEND)

Endpoint L RAM End Address Register
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_CEPDAT (CEPDAT)

Control-endpoint Data Buffer
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAT : Control-Endpoint Data Buffer \nControl endpoint data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported.
bits : 0 - 31 (32 bit)
access : read-write

USBD_CEPCTL (CEPCTL)

Control-endpoint Control and Status
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NAKCLR : No Acknowledge Control\nThis bit plays a crucial role in any control transfer. \nNote: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase. This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request

#1 : 1

This bit is set to one by the USB device controller, whenever a setup token is received. The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit

End of enumeration elements list.

STALLEN : Stall Enable Bit\nWhen this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter. This is typically used for response to invalid/unsupported requests. When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL. It is automatically cleared on receipt of a next setup-token. So, the local CPU need not write again to clear this bit.\nNote: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No sends a stall handshake in response to any in or out token thereafter

#1 : 1

The control endpoint sends a stall handshake in response to any in or out token thereafter

End of enumeration elements list.

ZEROLEN : Zero Packet Length\nThis bit is valid for Auto Validation mode only. \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No zero length packet to the host during Data stage to an IN token

#1 : 1

USB device controller can send a zero length packet to the host during Data stage to an IN token. This bit gets cleared once the zero length data packet is sent. So, the local CPU need not write again to clear this bit

End of enumeration elements list.

FLUSH : CEP-FLUSH Bit \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared

#1 : 1

The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared. This bit is self-cleaning

End of enumeration elements list.

USBD_CEPINTEN (CEPINTEN)

Control-endpoint Interrupt Enable
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUPTKIEN : Setup Token Interrupt Enable Bit \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The SETUP token interrupt in Control Endpoint Disabled

#1 : 1

The SETUP token interrupt in Control Endpoint Enabled

End of enumeration elements list.

SETUPPKIEN : Setup Packet Interrupt \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The SETUP packet interrupt in Control Endpoint Disabled

#1 : 1

The SETUP packet interrupt in Control Endpoint Enabled

End of enumeration elements list.

OUTTKIEN : Out Token Interrupt \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The OUT token interrupt in Control Endpoint Disabled

#1 : 1

The OUT token interrupt in Control Endpoint Enabled

End of enumeration elements list.

INTKIEN : In Token Interrupt \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The IN token interrupt in Control Endpoint Disabled

#1 : 1

The IN token interrupt in Control Endpoint Enabled

End of enumeration elements list.

PINGIEN : Ping Token Interrupt \n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The ping token interrupt in Control Endpoint Disabled

#1 : 1

The ping token interrupt Control Endpoint Enabled

End of enumeration elements list.

TXPKIEN : Data Packet Transmitted Interrupt \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

The data packet transmitted interrupt in Control Endpoint Disabled

#1 : 1

The data packet transmitted interrupt in Control Endpoint Enabled

End of enumeration elements list.

RXPKIEN : Data Packet Received Interrupt \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

The data received interrupt in Control Endpoint Disabled

#1 : 1

The data received interrupt in Control Endpoint Enabled

End of enumeration elements list.

NAKIEN : NAK Sent Interrupt \n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The NAK sent interrupt in Control Endpoint Disabled

#1 : 1

The NAK sent interrupt in Control Endpoint Enabled

End of enumeration elements list.

STALLIEN : STALL Sent Interrupt \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The STALL sent interrupt in Control Endpoint Disabled

#1 : 1

The STALL sent interrupt in Control Endpoint Enabled

End of enumeration elements list.

ERRIEN : USB Error Interrupt \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The USB Error interrupt in Control Endpoint Disabled

#1 : 1

The USB Error interrupt in Control Endpoint Enabled

End of enumeration elements list.

STSDONEIEN : Status Completion Interrupt \n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The Status Completion interrupt in Control Endpoint Disabled

#1 : 1

The Status Completion interrupt in Control Endpoint Enabled

End of enumeration elements list.

BUFFULLIEN : Buffer Full Interrupt \n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The buffer full interrupt in Control Endpoint Disabled

#1 : 1

The buffer full interrupt in Control Endpoint Enabled

End of enumeration elements list.

BUFEMPTYIEN : Buffer Empty Interrupt \n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The buffer empty interrupt in Control Endpoint Disabled

#1 : 1

The buffer empty interrupt in Control Endpoint Enabled

End of enumeration elements list.

USBD_CEPINTSTS (CEPINTSTS)

Control-endpoint Interrupt Status
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUPTKIF : Setup Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a Setup token is received

#1 : 1

A Setup token is received. Writing 1 clears this status bit

End of enumeration elements list.

SETUPPKIF : Setup Packet Interrupt \nThis bit must be cleared (by writing 1) before the next setup packet can be received. If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a Setup packet has been received from the host

#1 : 1

A Setup packet has been received from the host

End of enumeration elements list.

OUTTKIF : Out Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The control-endpoint does not received an OUT token from the host

#1 : 1

The control-endpoint receives an OUT token from the host

End of enumeration elements list.

INTKIF : In Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

The control-endpoint does not received an IN token from the host

#1 : 1

The control-endpoint receives an IN token from the host

End of enumeration elements list.

PINGIF : Ping Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The control-endpoint does not received a ping token from the host

#1 : 1

The control-endpoint receives a ping token from the host

End of enumeration elements list.

TXPKIF : Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same

#1 : 1

A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same

End of enumeration elements list.

RXPKIF : Data Packet Received Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host

#1 : 1

A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host

End of enumeration elements list.

NAKIF : NAK Sent Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a NAK-token is sent in response to an IN/OUT token

#1 : 1

A NAK-token is sent in response to an IN/OUT token

End of enumeration elements list.

STALLIF : STALL Sent Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a stall-token is sent in response to an IN/OUT token

#1 : 1

A stall-token is sent in response to an IN/OUT token

End of enumeration elements list.

ERRIF : USB Error Interrupt\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No error had occurred during the transaction

#1 : 1

An error had occurred during the transaction

End of enumeration elements list.

STSDONEIF : Status Completion Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a USB transaction has completed successfully

#1 : 1

The status stage of a USB transaction has completed successfully

End of enumeration elements list.

BUFFULLIF : Buffer Full Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

The control-endpoint buffer is not full

#1 : 1

The control-endpoint buffer is full

End of enumeration elements list.

BUFEMPTYIF : Buffer Empty Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

The control-endpoint buffer is not empty

#1 : 1

The control-endpoint buffer is empty

End of enumeration elements list.

USBD_CEPTXCNT (CEPTXCNT)

Control-endpoint In-transfer Data Count
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCNT : In-Transfer Data Count\nThere is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register. When zero is written into this field, a zero length packet is sent to the host. When the count written in the register is more than the MPS, the data sent will be of only MPS.
bits : 0 - 7 (8 bit)
access : read-write

USBD_CEPRXCNT (CEPRXCNT)

Control-endpoint Out-transfer Data Count
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXCNT : Out-Transfer Data Count \nThe USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
bits : 0 - 7 (8 bit)
access : read-only

USBD_CEPDATCNT (CEPDATCNT)

Control-endpoint Data Count
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATCNT : Control-Endpoint Data Count \nThe USB device controller maintains the count of the data of control-endpoint.
bits : 0 - 15 (16 bit)
access : read-only

USBD_SETUP1_0 (SETUP1_0)

Setup1 Setup0 Bytes
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SETUP0 : Setup Byte 0[7:0] This register provides byte 0 of the last setup packet received. For a Standard Device Request, the following bmRequestType information is returned. Bit 7(Direction): 0: Host to device 1: Device to host Bit 6-5 (Type): 00: Standard 01: Class 10: Vendor 11: Reserved Bit 4-0 (Recipient) 00000: Device 00001: Interface 00010: Endpoint 00011: Other Others: Reserved
bits : 0 - 7 (8 bit)
access : read-only

SETUP1 : Setup Byte 1[15:8]\nThis register provides byte 1 of the last setup packet received. For a Standard Device Request, the following bRequest Code information is returned. \n
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

#00000000 : 0

Get Status

#00000001 : 1

Clear Feature

#00000010 : 2

Reserved

#00000011 : 3

Set Feature

#00000100 : 4

Reserved

#00000101 : 5

Set Address

#00000110 : 6

Get Descriptor

#00000111 : 7

Set Descriptor

#00001000 : 8

Get Configuration

#00001001 : 9

Set Configuration

#00001010 : 10

Get Interface

#00001011 : 11

Set Interface

#00001100 : 12

Synch Frame

End of enumeration elements list.

USBD_SETUP3_2 (SETUP3_2)

Setup3 Setup2 Bytes
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SETUP2 : Setup Byte 2 [7:0]\nThis register provides byte 2 of the last setup packet received. For a Standard Device Request, the least significant byte of the wValue field is returned.
bits : 0 - 7 (8 bit)
access : read-only

SETUP3 : Setup Byte 3 [15:8]\nThis register provides byte 3 of the last setup packet received. For a Standard Device Request, the most significant byte of the wValue field is returned.
bits : 8 - 15 (8 bit)
access : read-only

USBD_SETUP5_4 (SETUP5_4)

Setup5 Setup4 Bytes
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SETUP4 : Setup Byte 4[7:0] \nThis register provides byte 4 of the last setup packet received. For a Standard Device Request, the least significant byte of the wIndex is returned.
bits : 0 - 7 (8 bit)
access : read-only

SETUP5 : Setup Byte 5[15:8] \nThis register provides byte 5 of the last setup packet received. For a Standard Device Request, the most significant byte of the wIndex field is returned.
bits : 8 - 15 (8 bit)
access : read-only

USBD_SETUP7_6 (SETUP7_6)

Setup7 Setup6 Bytes
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SETUP6 : Setup Byte 6[7:0] \nThis register provides byte 6 of the last setup packet received. For a Standard Device Request, the least significant byte of the wLength field is returned.
bits : 0 - 7 (8 bit)
access : read-only

SETUP7 : Setup Byte 7[15:8] \nThis register provides byte 7 of the last setup packet received. For a Standard Device Request, the most significant byte of the wLength field is returned.
bits : 8 - 15 (8 bit)
access : read-only

USBD_CEPBUFSTART (CEPBUFSTART)

Control Endpoint RAM Start Address Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR : Control-Endpoint Start Address\nThis is the start-address of the RAM space allocated for the control-endpoint.
bits : 0 - 11 (12 bit)
access : read-write

USBD_CEPBUFEND (CEPBUFEND)

Control Endpoint RAM End Address Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADDR : Control-Endpoint End Address\nThis is the end-address of the RAM space allocated for the control-endpoint.
bits : 0 - 11 (12 bit)
access : read-write

USBD_DMACTL (DMACTL)

DMA Control Status Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPNUM : DMA Endpoint Address Bits\nUsed to define the Endpoint Address
bits : 0 - 3 (4 bit)
access : read-write

DMARD : DMA Operation\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The operation is a DMA write (read from USB buffer). DMA will check endpoint data available count (USBD_EPxDATCNT) according to EPNM setting before to perform DMA write operation

#1 : 1

The operation is a DMA read (write to USB buffer)

End of enumeration elements list.

DMAEN : DMA Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

DMA function Disabled

#1 : 1

DMA function Enabled

End of enumeration elements list.

SGEN : Scatter Gather Function Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Scatter gather function Disabled

#1 : 1

Scatter gather function Enabled

End of enumeration elements list.

DMARST : Reset DMA State Machine\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset the DMA state machine

#1 : 1

Reset the DMA state machine

End of enumeration elements list.

USBD_DMACNT (DMACNT)

DMA Count Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACNT : DMA Transfer Count\nThe transfer count of the DMA operation to be performed is written to this register.
bits : 0 - 19 (20 bit)
access : read-write

USBD_EPADAT (EPADAT)

Endpoint A Data Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPDAT : Endpoint A~L Data Register \nEndpoint A~L data buffer for the buffer transaction (read or write).\nNote: Only word or byte access are supported.
bits : 0 - 31 (32 bit)
access : read-write

USBD_EPAINTSTS (EPAINTSTS)

Endpoint A Interrupt Status Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFFULLIF : Buffer Full \nFor an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write). For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).\nNote: This bit is read-only.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The endpoint packet buffer is not full

#1 : 1

The endpoint packet buffer is full

End of enumeration elements list.

BUFEMPTYIF : Buffer Empty\nFor an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes. \nNote: This bit is read-only.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

The endpoint buffer is not empty.\nThe currently selected buffer has not a count of 0

#1 : 1

The endpoint buffer is empty.\nThe currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read)

End of enumeration elements list.

SHORTTXIF : Short Packet Transferred Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

The length of the last packet was not less than the Maximum Packet Size (EPMPS)

#1 : 1

The length of the last packet was less than the Maximum Packet Size (EPMPS)

End of enumeration elements list.

TXPKIF : Data Packet Transmitted Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not a data packet is transmitted from the endpoint to the host

#1 : 1

A data packet is transmitted from the endpoint to the host

End of enumeration elements list.

RXPKIF : Data Packet Received Interrupt\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

No data packet is received from the host by the endpoint

#1 : 1

A data packet is received from the host by the endpoint

End of enumeration elements list.

OUTTKIF : Data OUT Token Interrupt\nNote: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

A Data OUT token has not been received from the host

#1 : 1

A Data OUT token has been received from the host. This bit also set by PING token (in high-speed only)

End of enumeration elements list.

INTKIF : Data IN Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not Data IN token has been received from the host

#1 : 1

A Data IN token has been received from the host

End of enumeration elements list.

PINGIF : PING Token Interrupt \nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

A Data PING token has not been received from the host

#1 : 1

A Data PING token has been received from the host

End of enumeration elements list.

NAKIF : USB NAK Sent\nNote: Write 1 to clear this bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

The last USB IN packet could be provided, and was acknowledged with an ACK

#1 : 1

The last USB IN packet could not be provided, and was acknowledged with a NAK

End of enumeration elements list.

STALLIF : USB STALL Sent\nNote: Write 1 to clear this bit to 0.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL

#1 : 1

The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL

End of enumeration elements list.

NYETIF : NYET Sent \nNote: Write 1 to clear this bit to 0.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

The space available in the RAM is sufficient to accommodate the next on coming data packet

#1 : 1

The space available in the RAM is not sufficient to accommodate the next on coming data packet

End of enumeration elements list.

ERRIF : ERR Sent \nNote: Write 1 to clear this bit to 0.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

No any error in the transaction

#1 : 1

There occurs any error in the transaction

End of enumeration elements list.

SHORTRXIF : Bulk Out Short Packet Received\nNote: Write 1 to clear this bit to 0.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

No bulk out short packet is received

#1 : 1

Received bulk out short packet (including zero length packet)

End of enumeration elements list.

USBD_EPAINTEN (EPAINTEN)

Endpoint A Interrupt Enable Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFFULLIEN : Buffer Full Interrupt \nWhen set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Buffer full interrupt Disabled

#1 : 1

Buffer full interrupt Enabled

End of enumeration elements list.

BUFEMPTYIEN : Buffer Empty Interrupt\nWhen set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Buffer empty interrupt Disabled

#1 : 1

Buffer empty interrupt Enabled

End of enumeration elements list.

SHORTTXIEN : Short Packet Transferred Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Short data packet interrupt Disabled

#1 : 1

Short data packet interrupt Enabled

End of enumeration elements list.

TXPKIEN : Data Packet Transmitted Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been received from the host.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data packet has been received from the host interrupt Disabled

#1 : 1

Data packet has been received from the host interrupt Enabled

End of enumeration elements list.

RXPKIEN : Data Packet Received Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data packet has been transmitted to the host interrupt Disabled

#1 : 1

Data packet has been transmitted to the host interrupt Enabled

End of enumeration elements list.

OUTTKIEN : Data OUT Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data OUT token interrupt Disabled

#1 : 1

Data OUT token interrupt Enabled

End of enumeration elements list.

INTKIEN : Data IN Token Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Data IN token interrupt Disabled

#1 : 1

Data IN token interrupt Enabled

End of enumeration elements list.

PINGIEN : PING Token Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a PING token has been received from the host.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PING token interrupt Disabled

#1 : 1

PING token interrupt Enabled

End of enumeration elements list.

NAKIEN : USB NAK Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a NAK token is sent to the host.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

NAK token interrupt Disabled

#1 : 1

NAK token interrupt Enabled

End of enumeration elements list.

STALLIEN : USB STALL Sent Interrupt Enable Bit \nWhen set, this bit enables a local interrupt to be set when a stall token is sent to the host.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

STALL token interrupt Disabled

#1 : 1

STALL token interrupt Enabled

End of enumeration elements list.

NYETIEN : NYET Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

NYET condition interrupt Disabled

#1 : 1

NYET condition interrupt Enabled

End of enumeration elements list.

ERRIEN : ERR Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

Error event interrupt Disabled

#1 : 1

Error event interrupt Enabled

End of enumeration elements list.

SHORTRXIEN : Bulk Out Short Packet Interrupt Enable Bit\nWhen set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Bulk out interrupt Disabled

#1 : 1

Bulk out interrupt Enabled

End of enumeration elements list.

USBD_EPADATCNT (EPADATCNT)

Endpoint A Data Available Count Register
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DATCNT : Data Count\nFor an IN endpoint (EPDIR(USBD_EPxCFG[3] is high.), this register returns the number of valid bytes in the IN endpoint packet buffer.\nFor an OUT endpoint (EPDIR(USBD_EPxCFG[3] is low.), this register returns the number of received valid bytes in the Host OUT transfer.
bits : 0 - 15 (16 bit)
access : read-only

DMALOOP : DMA Loop\nThis register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
bits : 16 - 30 (15 bit)
access : read-only

USBD_DMAADDR (DMAADDR)

AHB DMA Address Register
address_offset : 0x700 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAADDR : DMAADDR\nThe register specifies the address from which the DMA has to read / write. The address must WORD (32-bit) aligned.
bits : 0 - 31 (32 bit)
access : read-write

USBD_PHYCTL (PHYCTL)

USB PHY Control Register
address_offset : 0x704 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DPPUEN : DP Pull-Up\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Pull-up resistor on D+ Disabled

#1 : 1

Pull-up resistor on D+ Enabled

End of enumeration elements list.

PHYEN : PHY Suspend Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

The USB PHY is suspend

#1 : 1

The USB PHY is not suspend

End of enumeration elements list.

WKEN : Wake-Up Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

The wake-up function Disabled

#1 : 1

The wake-up function Enabled

End of enumeration elements list.

VBUSDET : VBUS Status\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

The VBUS is not detected yet

#1 : 1

The VBUS is detected

End of enumeration elements list.

USBD_EPARSPCTL (EPARSPCTL)

Endpoint A Response Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FLUSH : Buffer Flush \nWriting 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared. This bit is self-clearing. This bit should always be written after an configuration event.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The packet buffer is not flushed

#1 : 1

The packet buffer is flushed by user

End of enumeration elements list.

MODE : Mode Control\nThe two bits decide the operation mode of the in-endpoint. \n00: Auto-Validate Mode\n01: Manual-Validate Mode\n10: Fly Mode\n11: Reserved\nThese bits are not valid for an out-endpoint. The auto validate mode will be activated when the reserved mode is selected.
bits : 1 - 2 (2 bit)
access : read-write

TOGGLE : Endpoint Toggle This bit is used to clear the endpoint data toggle bit. Reading this bit returns the current state of the endpoint data toggle bit. The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host. Only when toggle bit is 1 , this bit can be written into the inversed write data bit[3].
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not clear the endpoint data toggle bit

#1 : 1

Clear the endpoint data toggle bit

End of enumeration elements list.

HALT : Endpoint Halt \nThis bit is used to send a STALL handshake as response to the token from the host. When an Endpoint Set Feature (ep_halt) is detected by the local CPU, it must write a '1' to this bit.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not send a STALL handshake as response to the token from the host

#1 : 1

Send a STALL handshake as response to the token from the host

End of enumeration elements list.

ZEROLEN : Zero Length\nThis bit is used to send a zero-length packet response to an IN-token. When this bit is set, a zero packet is sent to the host on reception of an IN-token. This bit gets cleared once the zero length data packet is sent.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

A zero packet is not sent to the host on reception of an IN-token

#1 : 1

A zero packet is sent to the host on reception of an IN-token

End of enumeration elements list.

SHORTTXEN : Short Packet Transfer Enable \nThis bit is applicable only in case of Auto-Validate Method. This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer. This bit gets cleared once the data packet is sent.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint

#1 : 1

Validate any remaining data in the buffer which is not equal to the MPS of the endpoint

End of enumeration elements list.

DISBUF : Buffer Disable Bit\nThis bit is used to receive unknown size OUT short packet. The received packet size is reference USBD_EPxDATCNT register.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Buffer Not Disabled when Bulk-OUT short packet is received

#1 : 1

Buffer Disabled when Bulk-OUT short packet is received

End of enumeration elements list.

USBD_EPAMPS (EPAMPS)

Endpoint A Maximum Packet Size Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPMPS : Endpoint Maximum Packet Size \nThis field determines the Maximum Packet Size of the Endpoint.
bits : 0 - 10 (11 bit)
access : read-write

USBD_EPATXCNT (EPATXCNT)

Endpoint A Transfer Count Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCNT : Endpoint Transfer Count\nFor IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.\nFor OUT endpoints, this field has no effect.
bits : 0 - 10 (11 bit)
access : read-write

USBD_GINTEN (GINTEN)

Interrupt Enable Low Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPACFG (EPACFG)

Endpoint A Configuration Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPEN : Endpoint Valid\nWhen set, this bit enables this endpoint. This bit has no effect on Endpoint 0, which is always enabled.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

The endpoint Disabled

#1 : 1

The endpoint Enabled

End of enumeration elements list.

EPTYPE : Endpoint Type\nThis field selects the type of this endpoint. Endpoint 0 is forced to a Control type. \n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved

#01 : 1

Bulk

#10 : 2

Interrupt

#11 : 3

Isochronous

End of enumeration elements list.

EPDIR : Endpoint Direction\nNote: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

out-endpoint (Host OUT to Device)

#1 : 1

in-endpoint (Host IN to Device)

End of enumeration elements list.

EPNUM : Endpoint Number\nThis field selects the number of the endpoint. Valid numbers 1 to 15.\nNote: Do not support two endpoints have same endpoint number.
bits : 4 - 7 (4 bit)
access : read-write

USBD_EPABUFSTART (EPABUFSTART)

Endpoint A RAM Start Address Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SADDR : Endpoint Start Address\nThis is the start-address of the RAM space allocated for the endpoint A~L.
bits : 0 - 11 (12 bit)
access : read-write

USBD_EPABUFEND (EPABUFEND)

Endpoint A RAM End Address Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EADDR : Endpoint End Address\nThis is the end-address of the RAM space allocated for the endpoint A~L.
bits : 0 - 11 (12 bit)
access : read-write

USBD_EPBDAT (EPBDAT)

Endpoint B Data Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBINTSTS (EPBINTSTS)

Endpoint B Interrupt Status Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBINTEN (EPBINTEN)

Endpoint B Interrupt Enable Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBDATCNT (EPBDATCNT)

Endpoint B Data Available Count Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBRSPCTL (EPBRSPCTL)

Endpoint B Response Control Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBMPS (EPBMPS)

Endpoint B Maximum Packet Size Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBTXCNT (EPBTXCNT)

Endpoint B Transfer Count Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBCFG (EPBCFG)

Endpoint B Configuration Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBBUFSTART (EPBBUFSTART)

Endpoint B RAM Start Address Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPBBUFEND (EPBBUFEND)

Endpoint B RAM End Address Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCDAT (EPCDAT)

Endpoint C Data Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCINTSTS (EPCINTSTS)

Endpoint C Interrupt Status Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCINTEN (EPCINTEN)

Endpoint C Interrupt Enable Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCDATCNT (EPCDATCNT)

Endpoint C Data Available Count Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCRSPCTL (EPCRSPCTL)

Endpoint C Response Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCMPS (EPCMPS)

Endpoint C Maximum Packet Size Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCTXCNT (EPCTXCNT)

Endpoint C Transfer Count Register
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCCFG (EPCCFG)

Endpoint C Configuration Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCBUFSTART (EPCBUFSTART)

Endpoint C RAM Start Address Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPCBUFEND (EPCBUFEND)

Endpoint C RAM End Address Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDDAT (EPDDAT)

Endpoint D Data Register
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDINTSTS (EPDINTSTS)

Endpoint D Interrupt Status Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDINTEN (EPDINTEN)

Endpoint D Interrupt Enable Register
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDDATCNT (EPDDATCNT)

Endpoint D Data Available Count Register
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDRSPCTL (EPDRSPCTL)

Endpoint D Response Control Register
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDMPS (EPDMPS)

Endpoint D Maximum Packet Size Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDTXCNT (EPDTXCNT)

Endpoint D Transfer Count Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDCFG (EPDCFG)

Endpoint D Configuration Register
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBD_EPDBUFSTART (EPDBUFSTART)

Endpoint D RAM Start Address Register
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

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USBD

Peripheral Memory Blocks

Registers

USBD_GINTSTS (GINTSTS)

USBD_BUSINTSTS (BUSINTSTS)

USBD_EPDBUFEND (EPDBUFEND)

USBD_EPEDAT (EPEDAT)

USBD_EPEINTSTS (EPEINTSTS)

USBD_EPEINTEN (EPEINTEN)

USBD_EPEDATCNT (EPEDATCNT)

USBD_EPERSPCTL (EPERSPCTL)

USBD_EPEMPS (EPEMPS)

USBD_EPETXCNT (EPETXCNT)

USBD_EPECFG (EPECFG)

USBD_EPEBUFSTART (EPEBUFSTART)

USBD_EPEBUFEND (EPEBUFEND)

USBD_EPFDAT (EPFDAT)

USBD_EPFINTSTS (EPFINTSTS)

USBD_EPFINTEN (EPFINTEN)

USBD_EPFDATCNT (EPFDATCNT)

USBD_EPFRSPCTL (EPFRSPCTL)

USBD_BUSINTEN (BUSINTEN)

USBD_EPFMPS (EPFMPS)

USBD_EPFTXCNT (EPFTXCNT)

USBD_EPFCFG (EPFCFG)

USBD_EPFBUFSTART (EPFBUFSTART)

USBD_EPFBUFEND (EPFBUFEND)

USBD_EPGDAT (EPGDAT)

USBD_EPGINTSTS (EPGINTSTS)

USBD_EPGINTEN (EPGINTEN)

USBD_EPGDATCNT (EPGDATCNT)

USBD_EPGRSPCTL (EPGRSPCTL)

USBD_EPGMPS (EPGMPS)

USBD_EPGTXCNT (EPGTXCNT)

USBD_EPGCFG (EPGCFG)

USBD_EPGBUFSTART (EPGBUFSTART)

USBD_EPGBUFEND (EPGBUFEND)

USBD_EPHDAT (EPHDAT)

USBD_OPER (OPER)

USBD_EPHINTSTS (EPHINTSTS)

USBD_EPHINTEN (EPHINTEN)

USBD_EPHDATCNT (EPHDATCNT)

USBD_EPHRSPCTL (EPHRSPCTL)

USBD_EPHMPS (EPHMPS)

USBD_EPHTXCNT (EPHTXCNT)

USBD_EPHCFG (EPHCFG)

USBD_EPHBUFSTART (EPHBUFSTART)

USBD_EPHBUFEND (EPHBUFEND)

USBD_EPIDAT (EPIDAT)

USBD_EPIINTSTS (EPIINTSTS)

USBD_EPIINTEN (EPIINTEN)

USBD_EPIDATCNT (EPIDATCNT)

USBD_EPIRSPCTL (EPIRSPCTL)

USBD_EPIMPS (EPIMPS)

USBD_EPITXCNT (EPITXCNT)

USBD_FRAMECNT (FRAMECNT)

USBD_EPICFG (EPICFG)

USBD_EPIBUFSTART (EPIBUFSTART)

USBD_EPIBUFEND (EPIBUFEND)

USBD_EPJDAT (EPJDAT)

USBD_EPJINTSTS (EPJINTSTS)

USBD_EPJINTEN (EPJINTEN)

USBD_EPJDATCNT (EPJDATCNT)

USBD_EPJRSPCTL (EPJRSPCTL)

USBD_EPJMPS (EPJMPS)

USBD_EPJTXCNT (EPJTXCNT)

USBD_EPJCFG (EPJCFG)

USBD_EPJBUFSTART (EPJBUFSTART)

USBD_EPJBUFEND (EPJBUFEND)

USBD_EPKDAT (EPKDAT)

USBD_EPKINTSTS (EPKINTSTS)

USBD_EPKINTEN (EPKINTEN)

USBD_FADDR (FADDR)

USBD_EPKDATCNT (EPKDATCNT)

USBD_EPKRSPCTL (EPKRSPCTL)

USBD_EPKMPS (EPKMPS)

USBD_EPKTXCNT (EPKTXCNT)

USBD_EPKCFG (EPKCFG)

USBD_EPKBUFSTART (EPKBUFSTART)