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address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
ASlot register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBOFF : First bit offset
bits : 0 - 4 (5 bit)
SLOTSZ : Slot size
bits : 6 - 7 (2 bit)
NBSLOT : Number of slots in an audio frame
bits : 8 - 11 (4 bit)
SLOTEN : Slot enable
bits : 16 - 31 (16 bit)
AInterrupt mask register2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRUDRIE : Overrun/underrun interrupt enable
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection interrupt enable
bits : 1 - 1 (1 bit)
WCKCFG : Wrong clock configuration interrupt enable
bits : 2 - 2 (1 bit)
FREQIE : FIFO request interrupt enable
bits : 3 - 3 (1 bit)
CNRDYIE : Codec not ready interrupt enable
bits : 4 - 4 (1 bit)
AFSDETIE : Anticipated frame synchronization detection interrupt enable
bits : 5 - 5 (1 bit)
LFSDET : Late frame synchronization detection interrupt enable
bits : 6 - 6 (1 bit)
AStatus register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRUDR : Overrun / underrun
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection
bits : 1 - 1 (1 bit)
WCKCFG : Wrong clock configuration flag. This bit is read only
bits : 2 - 2 (1 bit)
FREQ : FIFO request
bits : 3 - 3 (1 bit)
CNRDY : Codec not ready
bits : 4 - 4 (1 bit)
AFSDET : Anticipated frame synchronization detection
bits : 5 - 5 (1 bit)
LFSDET : Late frame synchronization detection
bits : 6 - 6 (1 bit)
FLVL : FIFO level threshold
bits : 16 - 18 (3 bit)
AClear flag register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRUDR : Clear overrun / underrun
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection flag
bits : 1 - 1 (1 bit)
WCKCFG : Clear wrong clock configuration flag
bits : 2 - 2 (1 bit)
CNRDY : Clear codec not ready flag
bits : 4 - 4 (1 bit)
CAFSDET : Clear anticipated frame synchronization detection flag
bits : 5 - 5 (1 bit)
LFSDET : Clear late frame synchronization detection flag
bits : 6 - 6 (1 bit)
AData register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
BConfiguration register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Audio block mode
bits : 0 - 1 (2 bit)
PRTCFG : Protocol configuration
bits : 2 - 3 (2 bit)
DS : Data size
bits : 5 - 7 (3 bit)
LSBFIRST : Least significant bit first
bits : 8 - 8 (1 bit)
CKSTR : Clock strobing edge
bits : 9 - 9 (1 bit)
SYNCEN : Synchronization enable
bits : 10 - 11 (2 bit)
MONO : Mono mode
bits : 12 - 12 (1 bit)
OutDri : Output drive
bits : 13 - 13 (1 bit)
SAIBEN : Audio block B enable
bits : 16 - 16 (1 bit)
DMAEN : DMA enable
bits : 17 - 17 (1 bit)
NODIV : No divider
bits : 19 - 19 (1 bit)
MCJDIV : Master clock divider
bits : 20 - 23 (4 bit)
MCKDIV : Master clock divider
bits : 20 - 23 (4 bit)
BConfiguration register 2
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold
bits : 0 - 2 (3 bit)
FFLUS : FIFO flush
bits : 3 - 3 (1 bit)
TRIS : Tristate management on data line
bits : 4 - 4 (1 bit)
MUTE : Mute
bits : 5 - 5 (1 bit)
MUTEVAL : Mute value
bits : 6 - 6 (1 bit)
MUTECN : Mute counter
bits : 7 - 12 (6 bit)
CPL : Complement bit
bits : 13 - 13 (1 bit)
COMP : Companding mode
bits : 14 - 15 (2 bit)
BFRCR
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRL : Frame length
bits : 0 - 7 (8 bit)
FSALL : Frame synchronization active level length
bits : 8 - 14 (7 bit)
FSDEF : Frame synchronization definition
bits : 16 - 16 (1 bit)
FSPOL : Frame synchronization polarity
bits : 17 - 17 (1 bit)
FSOFF : Frame synchronization offset
bits : 18 - 18 (1 bit)
BSlot register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBOFF : First bit offset
bits : 0 - 4 (5 bit)
SLOTSZ : Slot size
bits : 6 - 7 (2 bit)
NBSLOT : Number of slots in an audio frame
bits : 8 - 11 (4 bit)
SLOTEN : Slot enable
bits : 16 - 31 (16 bit)
BInterrupt mask register2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OVRUDRIE : Overrun/underrun interrupt enable
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection interrupt enable
bits : 1 - 1 (1 bit)
WCKCFG : Wrong clock configuration interrupt enable
bits : 2 - 2 (1 bit)
FREQIE : FIFO request interrupt enable
bits : 3 - 3 (1 bit)
CNRDYIE : Codec not ready interrupt enable
bits : 4 - 4 (1 bit)
AFSDETIE : Anticipated frame synchronization detection interrupt enable
bits : 5 - 5 (1 bit)
LFSDETIE : Late frame synchronization detection interrupt enable
bits : 6 - 6 (1 bit)
BStatus register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVRUDR : Overrun / underrun
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection
bits : 1 - 1 (1 bit)
WCKCFG : Wrong clock configuration flag
bits : 2 - 2 (1 bit)
FREQ : FIFO request
bits : 3 - 3 (1 bit)
CNRDY : Codec not ready
bits : 4 - 4 (1 bit)
AFSDET : Anticipated frame synchronization detection
bits : 5 - 5 (1 bit)
LFSDET : Late frame synchronization detection
bits : 6 - 6 (1 bit)
FLVL : FIFO level threshold
bits : 16 - 18 (3 bit)
BClear flag register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
OVRUDR : Clear overrun / underrun
bits : 0 - 0 (1 bit)
MUTEDET : Mute detection flag
bits : 1 - 1 (1 bit)
WCKCFG : Clear wrong clock configuration flag
bits : 2 - 2 (1 bit)
CNRDY : Clear codec not ready flag
bits : 4 - 4 (1 bit)
CAFSDET : Clear anticipated frame synchronization detection flag
bits : 5 - 5 (1 bit)
LFSDET : Clear late frame synchronization detection flag
bits : 6 - 6 (1 bit)
AConfiguration register 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Audio block mode
bits : 0 - 1 (2 bit)
PRTCFG : Protocol configuration
bits : 2 - 3 (2 bit)
DS : Data size
bits : 5 - 7 (3 bit)
LSBFIRST : Least significant bit first
bits : 8 - 8 (1 bit)
CKSTR : Clock strobing edge
bits : 9 - 9 (1 bit)
SYNCEN : Synchronization enable
bits : 10 - 11 (2 bit)
MONO : Mono mode
bits : 12 - 12 (1 bit)
OutDri : Output drive
bits : 13 - 13 (1 bit)
SAIAEN : Audio block A enable
bits : 16 - 16 (1 bit)
DMAEN : DMA enable
bits : 17 - 17 (1 bit)
NODIV : No divider
bits : 19 - 19 (1 bit)
MCJDIV : Master clock divider
bits : 20 - 23 (4 bit)
MCKDIV : Master clock divider
bits : 20 - 23 (4 bit)
BData register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
AConfiguration register 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTH : FIFO threshold
bits : 0 - 2 (3 bit)
FFLUS : FIFO flush
bits : 3 - 3 (1 bit)
TRIS : Tristate management on data line
bits : 4 - 4 (1 bit)
MUTE : Mute
bits : 5 - 5 (1 bit)
MUTEVAL : Mute value
bits : 6 - 6 (1 bit)
MUTECN : Mute counter
bits : 7 - 12 (6 bit)
CPL : Complement bit
bits : 13 - 13 (1 bit)
COMP : Companding mode
bits : 14 - 15 (2 bit)
AFRCR
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRL : Frame length
bits : 0 - 7 (8 bit)
FSALL : Frame synchronization active level length
bits : 8 - 14 (7 bit)
FSDEF : Frame synchronization definition
bits : 16 - 16 (1 bit)
FSPOL : Frame synchronization polarity
bits : 17 - 17 (1 bit)
FSOFF : Frame synchronization offset
bits : 18 - 18 (1 bit)
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