Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x408 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x800 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x820 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Shared Buffer (FIFO)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA Control and Status Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : DMA Engine Enable Bit\nIf this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.\nNote: If target abort is occurred, DMAEN will be cleared.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA Disabled
#1 : 1
DMA Enabled
End of enumeration elements list.
DMARST : Software Engine Reset\nNote: The software reset DMA related registers.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset internal state machine and pointers. The contents of control register will not be cleared. This bit will auto be cleared after few clock cycles
End of enumeration elements list.
SGEN : Scatter-Gather Function Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory)
#1 : 1
Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table. The format of these Pads' will be described later)
End of enumeration elements list.
DMABUSY : DMA Transfer Is In Progress\nThis bit indicates if SD Host is granted and doing DMA transfer or not.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA transfer is not in progress
#1 : 1
DMA transfer is in progress
End of enumeration elements list.
DMA Transfer Starting Address Register
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ORDER : Determined To The PAD Table Fetching Is In Order Or Out Of Order\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PAD table is fetched in order
#1 : 1
PAD table is fetched out of order
End of enumeration elements list.
DMASA : DMA Transfer Starting Address\nThis field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.\nIf DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
bits : 1 - 31 (31 bit)
access : read-write
DMA Transfer Byte Count Register
address_offset : 0x40C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BCNT : DMA Transfer Byte Count (Read Only)
This field indicates the remained byte count of DMA transfer. The value of this field is valid only when DMA is busy otherwise, it is 0.
bits : 0 - 25 (26 bit)
access : read-only
DMA Interrupt Enable Control Register
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABORTIEN : DMA Read/Write Target Abort Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt generation Disabled during DMA transfer
#1 : 1
Target abort interrupt generation Enabled during DMA transfer
End of enumeration elements list.
WEOTIEN : Wrong EOT Encountered Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generation Disabled when wrong EOT is encountered
#1 : 1
Interrupt generation Enabled when wrong EOT is encountered
End of enumeration elements list.
DMA Interrupt Status Register
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABORTIF : DMA Read/Write Target Abort Interrupt Flag\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
WEOTIF : Wrong EOT Encountered Interrupt Flag\nWhen DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EOT encountered before DMA transfer finished
#1 : 1
EOT encountered before DMA transfer finished
End of enumeration elements list.
Shared Buffer (FIFO)
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Shared Buffer (FIFO)
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Global Control and Status Register
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCTLRST : Software Engine Reset\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset SD host. The contents of control register will not be cleared. This bit will auto cleared after reset complete
End of enumeration elements list.
SDEN : Secure Digital Functionality Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD functionality disabled
#1 : 1
SD functionality enabled
End of enumeration elements list.
Global Interrupt Control Register
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTAIEN : DMA READ/WRITE Target Abort Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA READ/WRITE target abort interrupt generation disabled
#1 : 1
DMA READ/WRITE target abort interrupt generation enabled
End of enumeration elements list.
Global Interrupt Status Register
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTAIF : DMA READ/WRITE Target Abort Interrupt Flag (Read Only)\nThis bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation. When Target Abort is occurred, please reset all engine.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
SD Control and Status Register
address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEN : Command Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will output a command to SD card
End of enumeration elements list.
RIEN : Response Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will wait to receive a response from SD card
End of enumeration elements list.
DIEN : Data Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will wait to receive block data and the CRC16 value from SD card
End of enumeration elements list.
DOEN : Data Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will transfer block data and the CRC16 value to SD card
End of enumeration elements list.
R2EN : Response R2 Input Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7)
End of enumeration elements list.
CLK74OEN : Initial 74 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will output 74 clock cycles to SD card
End of enumeration elements list.
CLK8OEN : Generating 8 Clock Cycles Output Enable Bit\nNote: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect. (Please use CTLRST (SDH_CTL[14]) to clear this bit.)
#1 : 1
Enabled, SD host will output 8 clock cycles
End of enumeration elements list.
CLKKEEP0 : SD Clock Enable Control for Port 0\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD host decided when to output clock and when to disable clock output automatically
#1 : 1
SD clock always keeps free running
End of enumeration elements list.
CMDCODE : SD Command Code\nThis register contains the SD command code (0x00 - 0x3F).
bits : 8 - 13 (6 bit)
access : read-write
CTLRST : Software Engine Reset\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal state machine and counters. The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared). This bit will be auto cleared after few clock cycles
End of enumeration elements list.
DBW : SD Data Bus Width (For 1-Bit / 4-Bit Selection)\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data bus width is 1-bit
#1 : 1
Data bus width is 4-bit
End of enumeration elements list.
BLKCNT : Block Counts To Be Transferred Or Received\nThis field contains the block counts for data-in and data-out transfer. For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance. Don't fill 0x0 to this field.\nNote: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
bits : 16 - 23 (8 bit)
access : read-write
SDNWR : NWR Parameter For Block Write Operation\nThis value indicates the NWR parameter for data block write operation in SD clock counts. The actual clock cycle will be SDNWR+1.
bits : 24 - 27 (4 bit)
access : read-write
SDPORT : SD Port Selection\n
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
#00 : 0
Port 0 selected
#01 : 1
Port 1 selected
End of enumeration elements list.
CLKKEEP1 : SD Clock Enable Control for Port 1\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD host decided when to output clock and when to disable clock output automatically
#1 : 1
SD clock always keeps free running
End of enumeration elements list.
SD Command Argument Register
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARGUMENT : SD Command Argument\nThis register contains a 32-bit value specifies the argument of SD command from host controller to SD card. Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
bits : 0 - 31 (32 bit)
access : read-write
SD Interrupt Control Register
address_offset : 0x828 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKDIEN : Block Transfer Done Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD host will not generate interrupt when data-in (out) transfer done
#1 : 1
SD host will generate interrupt when data-in (out) transfer done
End of enumeration elements list.
CRCIEN : CRC7, CRC16 And CRC Status Error Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SD host will not generate interrupt when CRC7, CRC16 and CRC status is error
#1 : 1
SD host will generate interrupt when CRC7, CRC16 and CRC status is error
End of enumeration elements list.
CDIEN0 : SD0 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 0 is inserted or removed.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enabled
End of enumeration elements list.
CDIEN1 : SD1 Card Detection Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when card 1 is inserted or removed.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enabled
End of enumeration elements list.
RTOIEN : Response Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when receiving response or R2 time-out. Time-out value is specified at TOUT register.\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
DITOIEN : Data Input Time-Out Interrupt Enable Bit\nEnable/Disable interrupts generation of SD controller when data input time-out. Time-out value is specified at TOUT register.\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
WKIEN : Wake-Up Signal Generating Enable Bit\nEnable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CDSRC0 : SD0 Card Detect Source Selection\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
From SD0 card's DAT3 pin
#1 : 1
From GPIO pin
End of enumeration elements list.
CDSRC1 : SD1 Card Detect Source Selection\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
From SD1 card's DAT3 pin
#1 : 1
From GPIO pin
End of enumeration elements list.
SD Interrupt Status Register
address_offset : 0x82C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKDIF : Block Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that SD host has finished all data-in or data-out block transfer. If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not finished yet
#1 : 1
Done
End of enumeration elements list.
CRCIF : CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer. When CRC error is occurred, software should reset SD engine. Some response (ex. R3) doesn't have CRC7 information with it SD host will still calculate CRC7, get CRC error and set this flag. In this condition, software should ignore CRC error and clears this bit manually.
Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No CRC error is occurred
#1 : 1
CRC error is occurred
End of enumeration elements list.
CRC7 : CRC7 Check Status (Read Only)\nSD host will check CRC7 correctness during each response in. If that response does not contain CRC7 information (ex. R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fault
#1 : 1
OK
End of enumeration elements list.
CRC16 : CRC16 Check Status Of Data-In Transfer (Read Only)
SD host will check CRC16 correctness after data-in transfer.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Fault
#1 : 1
OK
End of enumeration elements list.
CRCSTS : CRC Status Value Of Data-Out Transfer (Read Only)\nSD host will record CRC status of data-out transfer. Software could use this value to identify what type of error is during data-out transfer.\n
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
#010 : 2
Positive CRC status
#101 : 5
Negative CRC status
#111 : 7
SD card programming error occurs
End of enumeration elements list.
DAT0STS : DAT0 Pin Status Of Current Selected SD Port (Read Only)\nThis bit is the DAT0 pin status of current selected SD port.
bits : 7 - 7 (1 bit)
access : read-only
CDIF0 : SD0 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 0 is inserted or removed. Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
No card is inserted or removed
#1 : 1
There is a card inserted in or removed from SD0
End of enumeration elements list.
CDIF1 : SD1 Card Detection Interrupt Flag (Read Only)\nThis bit indicates that SD card 1 is inserted or removed. Only when CDIEN1 (SDH_INTEN[9]) is set to 1, this bit is active.\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
No card is inserted or removed
#1 : 1
There is a card inserted in or removed from SD1
End of enumeration elements list.
RTOIF : Response Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not time-out
#1 : 1
Response time-out
End of enumeration elements list.
DITOIF : Data Input Time-Out Interrupt Flag (Read Only)\nThis bit indicates that SD host counts to time-out value when receiving data (waiting start bit).\nNote: This bit is read only, but can be cleared by writing '1' to it.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not time-out
#1 : 1
Data input time-out
End of enumeration elements list.
CDSTS0 : Card Detect Status Of SD0 (Read Only)\nThis bit indicates the card detect pin status of SD0, and is used for card detection. When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Card removed.\nCard inserted
#1 : 1
Card inserted.\nCard removed
End of enumeration elements list.
CDSTS1 : Card Detect Status Of SD1 (Read Only)\nThis bit indicates the card detect pin status of SD1, and is used for card detection. When there is a card inserted in or removed from SD1, software should check this bit to confirm if there is really a card insertion or removal.\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Card removed.\nCard inserted
#1 : 1
Card inserted.\nCard removed
End of enumeration elements list.
DAT1STS : DAT1 Pin Status Of SD Port (Read Only)\nThis bit indicates the DAT1 pin status of SD port.
bits : 18 - 18 (1 bit)
access : read-only
SD Receiving Response Token Register 0
address_offset : 0x830 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESPTK0 : SD Receiving Response Token 0\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This field contains response bit 47-16 of the response token.
bits : 0 - 31 (32 bit)
access : read-only
SD Receiving Response Token Register 1
address_offset : 0x834 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESPTK1 : SD Receiving Response Token 1\nSD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set. This register contains the bit 15-8 of the response token.
bits : 0 - 7 (8 bit)
access : read-only
SD Block Length Register
address_offset : 0x838 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BLKLEN : SD BLOCK LENGTH In Byte Unit\nAn 11-bit value specifies the SD transfer byte count of a block. The actual byte count is equal to BLKLEN+1.\nNote: The default SD block length is 512 bytes
bits : 0 - 10 (11 bit)
access : read-write
SD Response/Data-in Time-out Register
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOUT : SD Response/Data-In Time-Out Value\nA 24-bit value specifies the time-out counts of response and data input. SD host controller will wait start bit of response or data-in until this value reached. The time period depends on SD engine clock frequency. Do not write a small number into this field, or you may never get response or data due to time-out.\nNote: Filling 0x0 into this field will disable hardware time-out function.
bits : 0 - 23 (24 bit)
access : read-write
Shared Buffer (FIFO)
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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