\n

ACMP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ACMP_CTL0 (CTL0)

ACMP_VREF (VREF)

ACMP_CTL1 (CTL1)

ACMP_CTL2 (CTL2)

ACMP_STATUS (STATUS)


ACMP_CTL0 (CTL0)

Analog Comparator 0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_CTL0 ACMP_CTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPEN ACMPIE HYSEN ACMPOINV NEGSEL POSSEL

ACMPEN : Comparator 0 Enable Bit\nNote: The comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 0 Disabled

#1 : 1

Comparator 0 Enabled

End of enumeration elements list.

ACMPIE : Comparator 0 Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 0 interrupt Disabled

#1 : 1

Comparator 0 interrupt Enabled

End of enumeration elements list.

HYSEN : Comparator 0 Hysteresis Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 0 hysteresis Disabled (Default)

#1 : 1

Comparator 0 hysteresis Enabled (typical range is 20 mV)

End of enumeration elements list.

ACMPOINV : Comparator 0 Output Inverse\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 0 output inverse Disabled

#1 : 1

Comparator 0 output inverse Enabled

End of enumeration elements list.

NEGSEL : Comparator 0 Negative Input Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The source of comparator 0 negative input is from ACMP0_N pin

#1 : 1

The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 0 negative input

End of enumeration elements list.

POSSEL : Comparator 0 Positive Input Selection\nThe other options are reserved.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Input from ACMP0_P0

#001 : 1

Input from ACMP0_P1

#010 : 2

Input from ACMP0_P2

#011 : 3

Input from ACMP0_P3

#100 : 4

Input from OPA0

End of enumeration elements list.


ACMP_VREF (VREF)

Analog Comparator Reference Voltage Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_VREF ACMP_VREF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRVCTL CRVSSEL IREFSEL

CRVCTL : Comparator Reference Voltage Setting\n
bits : 0 - 3 (4 bit)
access : read-write

CRVSSEL : CRV Source Voltage Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

AVDD is selected as CRV source voltage

#1 : 1

Internal reference voltage is selected as CRV source voltage

End of enumeration elements list.

IREFSEL : Internal Reference Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Band-gap voltage is selected as internal reference

#1 : 1

CRV is selected as internal reference

End of enumeration elements list.


ACMP_CTL1 (CTL1)

Analog Comparator 1 Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_CTL1 ACMP_CTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPEN ACMPIE HYSEN ACMPOINV NEGSEL POSSEL

ACMPEN : Comparator 1 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 1 Disabled

#1 : 1

Comparator 1 Enabled

End of enumeration elements list.

ACMPIE : Comparator 1 Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 1 interrupt Disabled

#1 : 1

Comparator 1 interrupt Enabled

End of enumeration elements list.

HYSEN : Comparator 1 Hysteresis Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 1 hysteresis Disabled (Default)

#1 : 1

Comparator 1 hysteresis Enabled (typical range is 20 mV)

End of enumeration elements list.

ACMPOINV : Comparator 1 Output Inverse Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 1 output inverse Disabled

#1 : 1

Comparator 1 output inverse Enabled

End of enumeration elements list.

NEGSEL : Comparator 1 Negative Input Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The source of comparator 1 negative input is from ACMP1_N pin

#1 : 1

The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 1 negative input

End of enumeration elements list.

POSSEL : Comparator 1 Positive Input Selection\nThe other options are reserved.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Input from ACMP1_P0

#001 : 1

Input from ACMP1_P1

#010 : 2

Input from ACMP1_P2

#011 : 3

Input from ACMP1_P3

#100 : 4

Input from OPA1

End of enumeration elements list.


ACMP_CTL2 (CTL2)

Analog Comparator 2 Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_CTL2 ACMP_CTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPEN ACMPIE HYSEN ACMPOINV NEGSEL POSSEL

ACMPEN : Comparator 2 Enable Bit\nThe comparator output needs to wait 2 us stable time after ACMPEN is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 2 Disabled

#1 : 1

Comparator 2 Enabled

End of enumeration elements list.

ACMPIE : Comparator 2 Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 2 interrupt Disabled

#1 : 1

Comparator 2 interrupt Enabled

End of enumeration elements list.

HYSEN : Comparator 2 Hysteresis Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 2 hysteresis Disabled (Default)

#1 : 1

Comparator 2 hysteresis Enabled (typical range is 20 mV)

End of enumeration elements list.

ACMPOINV : Comparator 2 Output Inverse Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Comparator 2 output inverse Disabled

#1 : 1

Comparator 2 output inverse Enabled

End of enumeration elements list.

NEGSEL : Comparator 2 Negative Input Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

The source of comparator 2 negative input is from ACMP2_N pin

#1 : 1

The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 2 negative input

End of enumeration elements list.

POSSEL : Comparator 2 Positive Input Selection\nThe other options are reserved.
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

#000 : 0

Input from ACMP2_P0

#001 : 1

Input from ACMP2_P1

#010 : 2

Input from ACMP2_P2

#011 : 3

Input from ACMP2_P3

End of enumeration elements list.


ACMP_STATUS (STATUS)

Analog Comparator Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACMP_STATUS ACMP_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACMPIF0 ACMPIF1 ACMPIF2 ACMPO0 ACMPO1 ACMPO2

ACMPIF0 : Comparator 0 Flag\nThis bit is set by hardware whenever the comparator 0 output changes state. This will cause an interrupt if ACMP_CTL0[1] is set to 1.\nWrite 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

ACMPIF1 : Comparator 1 Flag\nThis bit is set by hardware whenever the comparator 1 output changes state. This will cause an interrupt if ACMP_CTL1[1] is set to 1.\nWrite 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

ACMPIF2 : Comparator 2 Flag\nThis bit is set by hardware whenever the comparator 2 output changes state. This will cause an interrupt if ACMP_CTL2[1] is set to 1.\nWrite 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

ACMPO0 : Comparator 0 Output\n
bits : 3 - 3 (1 bit)
access : read-write

ACMPO1 : Comparator 1 Output\n
bits : 4 - 4 (1 bit)
access : read-write

ACMPO2 : Comparator 2 Output\n
bits : 5 - 5 (1 bit)
access : read-write



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