Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x13C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x248 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x288 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C8 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x348 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
Crypto Interrupt Enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIEN : AES Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.\nIn Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES interrupt Disabled
#1 : 1
AES interrupt Enabled
End of enumeration elements list.
AESERRIEN : AES Error Flag Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES error interrupt flag Disabled
#1 : 1
AES error interrupt flag Enabled
End of enumeration elements list.
TDESIEN : TDES/DES Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.\nIn Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES interrupt Disabled
#1 : 1
TDES/DES interrupt Enabled
End of enumeration elements list.
TDESERRIEN : TDES/DES Error Flag Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES error interrupt flag Disabled
#1 : 1
TDES/DES error interrupt flag Enabled
End of enumeration elements list.
PRNGIEN : PRNG Interrupt Enable Bit \n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG interrupt Disabled
#1 : 1
PRNG interrupt Enabled
End of enumeration elements list.
SHAIEN : SHA Interrupt Enable Bit\nIn DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine. In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA interrupt Disabled
#1 : 1
SHA interrupt Enabled
End of enumeration elements list.
SHAERRIEN : SHA Error Interrupt Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA error interrupt flag Disabled
#1 : 1
SHA error interrupt flag Enabled
End of enumeration elements list.
PRNG Generated Key0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
KEYx : Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
bits : 0 - 31 (32 bit)
access : read-only
AES Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : AES Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start AES engine. BUSY flag will be set
End of enumeration elements list.
STOP : AES Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop AES engine
End of enumeration elements list.
KEYSZ : AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
bits : 2 - 3 (2 bit)
access : read-write
DMALAST : AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : AES Engine DMA With Cascade Mode\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES DMA engine Disabled
#1 : 1
AES DMA engine Enabled
End of enumeration elements list.
OPMODE : AES Engine Operation Modes\n
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
0x10 : 16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x11 : 17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x12 : 18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
End of enumeration elements list.
ENCRPT : AES Encryption/Decryption\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES engine executes decryption operation
#1 : 1
AES engine executes encryption operation
End of enumeration elements list.
OUTSWAP : AES Engine Output Data Swap \n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : AES Engine Input Data Swap \n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : AES Engine Working Channel\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key
Writing 0 to CRPT_AES_CTL [31] and 10110 to CRPT_AES_CTL [30:26] is to unprotect the AES key.
The KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Protect the content of the AES key from reading. The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
End of enumeration elements list.
AES Engine Flag
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : AES Engine Busy\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The AES engine is idle or finished
#1 : 1
The AES engine is under processing
End of enumeration elements list.
INBUFEMPTY : AES Input Buffer Empty\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the AES engine to process
#1 : 1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : AES Input Buffer Full Flag\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES input buffer is not full. Software can feed the data into the AES engine
#1 : 1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : AES Input Buffer Error Flag\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the AES engine
End of enumeration elements list.
CNTERR : AES_CNT Setting Error\n
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error in AES_CNT setting
#1 : 1
AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode
End of enumeration elements list.
OUTBUFEMPTY : AES Out Buffer Empty\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
AES output buffer is empty. Software cannot get data from AES_DATA_OUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
End of enumeration elements list.
OUTBUFFULL : AES Out Buffer Full Flag\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not full
#1 : 1
AES output buffer is full, and software needs to get data from AES_DATA_OUT. Otherwise, the AES engine will be pending since the output buffer is full
End of enumeration elements list.
OUTBUFERR : AES Out Buffer Error Flag\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting the result from AES engine
End of enumeration elements list.
BUSERR : AES DMA Access Bus Error Flag\n
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and AES engine
End of enumeration elements list.
AES Engine Data Input Port Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
AES Engine Data Output Port Register
address_offset : 0x10C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRPT_AES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
AES Key Word 0 Register for Channel 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : CRPT_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. {CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation. {CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation. {CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 1 Register for Channel 0
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 0
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 0
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 0
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 0
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 0
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 0
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV : CRPT_AESn_IVx\nFour initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
AES Initial Vector Word 1 Register for Channel 0
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 0
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 0
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 0
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRPT_AESn_SADDR before triggering START.\nThe value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES DMA Destination Address Register for Channel 0
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. \nThe value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES Byte Count Register for Channel 0
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : AES Byte Count\nThe CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_AESn_CNT can be read and written. Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRPT_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block. Operations that are less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 0 Register for Channel 1
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 1
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 1
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 1
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 1
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 1
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 1
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 1
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 1
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 1
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 1
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 1
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 1
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 1
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 1
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 2
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 2
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 2
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 2
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 2
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 2
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 2
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 2
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 2
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 2
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 2
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 2
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 2
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 2
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 2
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 3
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 3
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 3
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 3
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 3
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 3
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 3
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 3
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 3
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 3
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 3
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 3
address_offset : 0x1F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 3
address_offset : 0x1F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 3
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 3
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key4
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : TDES/DES Engine Start\nNote: The bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start TDES/DES engine. The flag BUSY would be set
End of enumeration elements list.
STOP : TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop TDES/DES engine
End of enumeration elements list.
TMODE : TDES/DES Engine Operating Mode\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set DES mode for TDES/DES engine
#1 : 1
Set Triple DES mode for TDES/DES engine
End of enumeration elements list.
_3KEYS : TDES/DES Key Number\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select KEY1 and KEY2 in TDES/DES engine
#1 : 1
Triple keys in TDES/DES engine Enabled
End of enumeration elements list.
DMALAST : TDES/DES Engine Start For The Last Block \nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last block of data.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : TDES/DES Engine DMA With Cascade Mode\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES_DMA engine Disabled
#1 : 1
TDES_DMA engine Enabled
End of enumeration elements list.
OPMODE : TDES/DES Engine Operation Mode\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode)
0x01 : 1
CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
End of enumeration elements list.
ENCRPT : TDES/DES Encryption/Decryption\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES engine executes decryption operation
#1 : 1
TDES engine executes encryption operation
End of enumeration elements list.
BLKSWAP : TDES/DES Engine Block Double Word Endian Swap \n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order, e.g. {WORD_H, WORD_L}
#1 : 1
When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}
End of enumeration elements list.
OUTSWAP : TDES/DES Engine Output Data Swap \n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : TDES/DES Engine Input Data Swap \n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : TDES/DES Engine Working Channel\n
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key
Writing 0 to CRPT_TDES_CTL [31] and 10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
The KEYUNPRT can be read and written. When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
This bit is to protect the content of TDES key from reading. The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L. Once it is set, it can be cleared by asserting KEYUNPRT. The key content would be cleared as well
End of enumeration elements list.
TDES/DES Engine Flag
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : TDES/DES Engine Busy \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES engine is idle or finished
#1 : 1
TDES/DES engine is under processing
End of enumeration elements list.
INBUFEMPTY : TDES/DES In Buffer Empty\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the TDES/DES engine to process
#1 : 1
TDES/DES input buffer is empty. Software needs to feed data to the TDES/DES engine. Otherwise, the TDES/DES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : TDES/DES In Buffer Full Flag\n
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine
#1 : 1
TDES input buffer is full. Software cannot feed data to the TDES/DES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : TDES/DES In Buffer Error Flag\n
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the TDES/DES engine
End of enumeration elements list.
OUTBUFEMPTY : TDES/DES Output Buffer Empty Flag\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty
End of enumeration elements list.
OUTBUFFULL : TDES/DES Output Buffer Full Flag\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not full
#1 : 1
TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. Otherwise, the TDES/DES engine will be pending since output buffer is full
End of enumeration elements list.
OUTBUFERR : TDES/DES Out Buffer Error Flag\n
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting test result from TDES/DES engine
End of enumeration elements list.
BUSERR : TDES/DES DMA Access Bus Error Flag\n
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and TDES/DES engine
End of enumeration elements list.
TDES/DES Key 1 High Word Register for Channel 0
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYH_KEYL : TDES/DES Key X High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit registers to store a security key. The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0].
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Key 1 Low Word Register for Channel 0
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 0
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 0
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 0
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 0
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 0
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVH_IVL : TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. IV is Nonce counter for TDES/DES engine in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Initial Vector Low Word Register for Channel 0
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 0
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The CRPT_TDESn_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRPT_TDESn_SADDR are ignored.\nTDES_SADR can be read and written. Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRPT_TDESn_SADDR before triggering START.\nCRPT_TDESn_SADDR and CRPT_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES DMA Destination Address Register for Channel 0
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO. The CRPT_TDESn_DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of CRPT_TDESn_DADDR are ignored.\nTDES_DADR can be read and written. Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_DADDR will be updated later on. Consequently, software can prepare the destination address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRPT_TDESn_DADDR before triggering START. \nCRPT_TDESn_SADDR and CRPT_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Byte Count Register for Channel 0
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : TDES/DES Byte Count \nThe CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_TDESn_CNT can be read and written. Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRPT_TDESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next TDES /DES operation.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Input Data Word Register
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Output Data Word Register
address_offset : 0x238 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
PRNG Generated Key5
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 1
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 1
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 1
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 1
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 1
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 1
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 1
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 1
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 1
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 1
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 1
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key6
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 2
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 2
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 2
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 2
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 2
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 2
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 2
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 2
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 2
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 2
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 2
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key7
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 3
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 3
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 3
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 3
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 3
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 3
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 3
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 3
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 3
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 3
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 3
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : SHA Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start SHA engine. BUSY flag will be set
End of enumeration elements list.
STOP : SHA Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop SHA engine
End of enumeration elements list.
DMALAST : SHA Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last byte of data.
bits : 5 - 5 (1 bit)
access : read-write
DMAEN : SHA Engine DMA Enable Bit\nThe SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA_DMA engine Disabled
#1 : 1
SHA_DMA engine Enabled
End of enumeration elements list.
OPMODE : SHA Engine Operation Modes\nNote: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
SHA160
#100 : 4
SHA256
#101 : 5
SHA224
End of enumeration elements list.
OUTSWAP : SHA Engine Output Data Swap\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : SHA Engine Input Data Swap\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
SHA Status Flag
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : SHA Engine Busy \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA engine is idle or finished
#1 : 1
SHA engine is busy
End of enumeration elements list.
DMABUSY : SHA Engine DMA Busy Flag\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA DMA engine is idle or finished
#1 : 1
SHA DMA engine is busy
End of enumeration elements list.
DMAERR : SHA Engine DMA Error Flag\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Show the SHA engine access normal
#1 : 1
Show the SHA engine access error
End of enumeration elements list.
DATINREQ : SHA Non-DMA Mode Data Input Request\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
Request SHA Non-DMA mode data input
End of enumeration elements list.
SHA Digest Message 0
address_offset : 0x308 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DGST : SHA Digest Message Word\nFor SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.\nFor SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.\nFor SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
bits : 0 - 31 (32 bit)
access : read-only
SHA Digest Message 1
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 2
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 3
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 4
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 5
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 6
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Digest Message 7
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA Key Byte Count Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYCNT : SHA Key Byte Count\nThe CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation. But the value of CRPT_SHA_KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA operation.
bits : 0 - 31 (32 bit)
access : read-write
SHA DMA Source Address Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : SHA DMA Source Address\nThe SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO. The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored.\nCRPT_SHA_SADDR can be read and written. Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRPT_SHA_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA operation.\nIn DMA mode, software can update the next TDES_SADR before triggering START.\nCRPT_SHA_SADDR and CRPT_SHA_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
SHA Byte Count Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMACNT : SHA Operation Byte Count\nThe CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode. The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRPT_SHA_DMACNT can be read and written. Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation. But the value of CRPT_SHA_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA operation.\nIn Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
SHA Engine Non-dMA Mode Data Input Port Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : SHA Engine Input Port\nCPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1.
bits : 0 - 31 (32 bit)
access : read-write
Crypto Interrupt Flag
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIF : AES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES interrupt
#1 : 1
AES encryption/decryption done interrupt
End of enumeration elements list.
AESERRIF : AES Error Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES error
#1 : 1
AES encryption/decryption done interrupt
End of enumeration elements list.
TDESIF : TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES interrupt
#1 : 1
TDES/DES encryption/decryption done interrupt
End of enumeration elements list.
TDESERRIF : TDES/DES Error Flag\nThis bit includes the operating and setting error. The detailed flag is shown in the TDES _FLAG register. This includes operating and setting error.\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES error
#1 : 1
TDES/DES encryption/decryption error interrupt
End of enumeration elements list.
PRNGIF : PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PRNG interrupt
#1 : 1
PRNG key generation done interrupt
End of enumeration elements list.
SHAIF : SHA Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA interrupt
#1 : 1
SHA operation done interrupt
End of enumeration elements list.
SHAERRIF : SHA Error Flag\nThis register includes operating and setting error. The detail flag is shown in SHA _FLAG register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA error
#1 : 1
SHA error interrupt
End of enumeration elements list.
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode. The feedback register is for CBC, CFB, and OFB mode.\nTDES/DES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to this register in the same channel operation. Then can continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start PRNG Engine\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop PRNG engine
#1 : 1
Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated
End of enumeration elements list.
SEEDRLD : Reload New Seed For PRNG Engine\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Generating key based on the current seed
#1 : 1
Reload new seed
End of enumeration elements list.
KEYSZ : PRNG Generate Key Size\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
64 bits
#01 : 1
128 bits
#10 : 2
192 bits
#11 : 3
256 bits
End of enumeration elements list.
BUSY : PRNG Busy (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PRNG engine is idle
#1 : 1
Indicate that the PRNG engine is generating CRPT_PRNG_KEYx
End of enumeration elements list.
Seed for PRNG
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SEED : Seed For PRNG (Write Only)\nThe bits store the seed for PRNG engine.
bits : 0 - 31 (32 bit)
access : write-only
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