ADC_DAT0 (DAT0)

ADC_DAT4 (DAT4)

ADC_DAT5 (DAT5)

ADC_DAT6 (DAT6)

ADC_DAT7 (DAT7)

ADC_DAT8 (DAT8)

ADC_DAT9 (DAT9)

ADC_DAT10 (DAT10)

ADC_DAT11 (DAT11)

ADC_DAT12 (DAT12)

ADC_DAT13 (DAT13)

ADC_DAT1 (DAT1)

ADC_CTL (CTL)

ADC_CHEN (CHEN)

ADC_CMP0 (CMP0)

ADC_CMP1 (CMP1)

ADC_STATUS0 (STATUS0)

ADC_STATUS1 (STATUS1)

ADC_CURDAT (CURDAT)

ADC_DAT2 (DAT2)

ADC_DAT3 (DAT3)

RESULT : A/D Conversion Result\nThis field contains conversion result of ADC.\nWhen DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
bits : 0 - 15 (16 bit)
access : read-only

OV : Overrun Flag (Read Only)\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. It is cleared by hardware after ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag (Read Only)\nThis bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADCEN : ADC Enable Bit\nBefore disabling ADC clock, this bit should be cleared to 0 by software.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIEN : ADC Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : ADC Operation Mode\nWhen changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGSEL : External Hardware Trigger Source\nSoftware should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).\nIn hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGCOND : External Pin Trigger Conditions\nThese two bits decide external pin (STADC) trigger event. The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HWTRGEN : External Hardware Trigger Enable Bit\nEnable or disable hardware triggering of A/D conversion. The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register.\nADC hardware trigger function is only supported in single-cycle scan mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMAEN : PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.\nWhen PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIFFEN : Differential Input Mode Enable Bit\nIn differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]). The conversion result will be placed to the corresponding data register of the enabled channel.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D Conversion Start\nThe SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger. The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMTRGDLY : PWM Trigger Delay Time\nSetting this field will delay ADC start conversion time after PWM trigger comes.\nPWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])
bits : 16 - 23 (8 bit)
access : read-write

DMOF : ADC Differential Input Mode Output Format\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN : Analog Input Channel Enable Bit\nSet CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11). If DIFFEN bit is set to 1, only the even number channels need to be enabled \n
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADBGEN : Internal Band-Gap Selection\nADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADTSEN : Internal Temperature Sensor Selection\nADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPEN : Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\n
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMCNT : Compare Match Count\nWhen the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1. When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Compared Data\nWhen DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format. CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format.\nWhen DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format. CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format.
bits : 16 - 27 (12 bit)
access : read-write

ADIF : ADC Interrupt Flag\nA status flag that indicates the end of A/D conversion.\nADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:\n1. When A/D conversion ends in Single mode\n2. When A/D conversion ends on all specified channels in Scan mode\nNote: This flag can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE (Read Only)\nThis bit is mirror of as SWTRG (ADC_CTL[11]) bit.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 7 (4 bit)
access : read-only

VALID : Data Valid Flag (Read Only)\nIt is a mirror of VALID (ADC_DATx[17]) bit.
bits : 0 - 13 (14 bit)
access : read-only

OV : Overrun Flag (Read Only)\nIt is a mirror to OV (ADC_DATx[16]) bit.
bits : 16 - 29 (14 bit)
access : read-only

CURDAT : ADC PDMA Current Transfer Data Bit (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.
bits : 0 - 17 (18 bit)
access : read-only