Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
A/D Data Register 0 for SAMPLE00
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : A/D Conversion Result\nThis field contains 12 bits conversion result.
bits : 0 - 11 (12 bit)
access : read-only
OV : Overrun Flag\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result
#1 : 1
Data in RESULT (EADC_ADnDATx[11:0]) is overwrite
End of enumeration elements list.
VALID : Valid Flag\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT (EADC_ADnDATx[11:0]) is not valid
#1 : 1
Data in RESULT (EADC_ADnDATx[11:0]) is valid
End of enumeration elements list.
A/D Data Register 4 for SAMPLE04
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 0 for SAMPLE00
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : A/D Conversion Result\nThis field contains 12 bits conversion result.
bits : 0 - 11 (12 bit)
access : read-only
VALID : Valid Flag\nThis bit is set to 1 when corresponding SAMPLE MODULE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid
#1 : 1
Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid
End of enumeration elements list.
A/D Double Data Register 1 for SAMPLE01
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 2 for SAMPLE02
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 3 for SAMPLE03
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 0 for SAMPLE10
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 1 for SAMPLE11
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 2 for SAMPLE12
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Data Register 3 for SAMPLE13
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Buffer Mode Select
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD0DBM0 : Double Buffer Mode For SAMPLE00 \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE00 has one sample result register. (default)
#1 : 1
SAMPLE00 has two sample result registers
End of enumeration elements list.
AD0DBM1 : Double Buffer Mode For SAMPLE01 \n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE01 has one sample result register. (default)
#1 : 1
SAMPLE01 has two sample result registers
End of enumeration elements list.
AD0DBM2 : Double Buffer Mode For SAMPLE02 \n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE02 has one sample result register. (default).
#1 : 1
SAMPLE02 has two sample result registers
End of enumeration elements list.
AD0DBM3 : Double Buffer Mode For SAMPLE03 \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE03 has one sample result register. (default)
#1 : 1
SAMPLE03 has two sample result registers
End of enumeration elements list.
AD1DBM0 : Double Buffer Mode For SAMPLE10 \n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE10 has one sample result register. (default)
#1 : 1
SAMPLE10 has two sample result registers
End of enumeration elements list.
AD1DBM1 : Double Buffer Mode For SAMPLE11 \n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE11 has one sample result register. (default)
#1 : 1
SAMPLE11 has two sample result registers
End of enumeration elements list.
AD1DBM2 : Double Buffer Mode For SAMPLE12 \n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE12 has one sample result register. (default).
#1 : 1
SAMPLE12 has two sample result registers
End of enumeration elements list.
AD1DBM3 : Double Buffer Mode For SAMPLE13 \n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE13 has one sample result register. (default)
#1 : 1
SAMPLE13 has two sample result registers
End of enumeration elements list.
A/D Interrupt 0 Source Enable Control Register
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD0SPIE0 : SAMPLE00 Interrupt Mask Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE00 interrupt mask Disabled
#1 : 1
SAMPLE00 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE1 : SAMPLE01 Interrupt Mask Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE01 interrupt mask Disabled
#1 : 1
SAMPLE01 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE2 : SAMPLE02 Interrupt Mask Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE02 interrupt mask Disabled
#1 : 1
SAMPLE02 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE3 : SAMPLE03 Interrupt Mask Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE03 interrupt mask Disabled
#1 : 1
SAMPLE03 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE4 : SAMPLE04 Interrupt Mask Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE04 interrupt mask Disabled
#1 : 1
SAMPLE04 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE5 : SAMPLE05 Interrupt Mask Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE05 interrupt mask Disabled
#1 : 1
SAMPLE05 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE6 : SAMPLE06 Interrupt Mask Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE06 interrupt mask Disabled
#1 : 1
SAMPLE06 interrupt mask Enabled
End of enumeration elements list.
AD0SPIE7 : SAMPLE07 Interrupt Mask Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE07 interrupt mask Disabled
#1 : 1
SAMPLE07 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE0 : SAMPLE10 Interrupt Mask Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE10 interrupt mask Disabled
#1 : 1
SAMPLE10 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE1 : SAMPLE11 Interrupt Mask Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE11 interrupt mask Disabled
#1 : 1
SAMPLE11 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE2 : SAMPLE12 Interrupt Mask Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE12 interrupt mask Disabled
#1 : 1
SAMPLE12 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE3 : SAMPLE13 Interrupt Mask Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE13 interrupt mask Disabled
#1 : 1
SAMPLE13 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE4 : SAMPLE14 Interrupt Mask Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE14 interrupt mask Disabled
#1 : 1
SAMPLE14 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE5 : SAMPLE15 Interrupt Mask Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE15 interrupt mask Disabled
#1 : 1
SAMPLE15 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE6 : SAMPLE16 Interrupt Mask Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE16 interrupt mask Disabled
#1 : 1
SAMPLE16 interrupt mask Enabled
End of enumeration elements list.
AD1SPIE7 : SAMPLE17 Interrupt Mask Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE17 interrupt mask Disabled
#1 : 1
SAMPLE17 interrupt mask Enabled
End of enumeration elements list.
A/D Interrupt 1 Source Enable Control Register
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Interrupt 2 Source Enable Control Register
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 5 for SAMPLE05
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Interrupt 3 Source Enable Control Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE00
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM00REN : EPWM0_CH0 Rising Edge Trigger Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM00FEN : EPWM0_CH0 Falling Edge Trigger Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM00PEN : EPWM0_CH0 Period Trigger Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM00CEN : EPWM0_CH0 Center Trigger Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM02REN : EPWM0_CH2 Rising Edge Trigger Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM02FEN : EPWM0_CH2 Falling Edge Trigger Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM02PEN : EPWM0_CH2 Period Trigger Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM02CEN : EPWM0_CH2 Center Trigger Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM04REN : EPWM0_CH4 Rising Edge Trigger Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM04FEN : EPWM0_CH4 Falling Rdge Trigger Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM04PEN : EPWM0_CH4 Period Trigger Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM04CEN : EPWM0_CH4 Center Trigger Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM10REN : EPWM1_CH0 Rising Edge Trigger Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM10FEN : EPWM1_CH0 Falling Edge Trigger Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM10PEN : EPWM1_CH0 Period Trigger Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM10CEN : EPWM1_CH0 Center Trigger Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM12REN : EPWM1_CH2 Rising Edge Trigger Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM120FEN : EPWM1_CH2 Falling Edge Trigger Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM12PEN : EPWM1_CH2 Period Trigger Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM12CEN : EPWM1_CH2 Center Trigger Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM14REN : EPWM1_CH4 Rising Edge Trigger Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM14FEN : EPWM1_CH4 Falling Edge Trigger Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM14PEN : EPWM1_CH4 Period Trigger Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
EPWM14CEN : EPWM1_CH4 Center Trigger Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM00REN : PWM0_CH0 Rising Edge Trigger Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM00FEN : PWM0_CH0 Falling Edge Trigger Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM00PEN : PWM0_CH0 Period Trigger Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM00CEN : PWM0_CH0 Center Trigger Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM01REN : PWM0_CH1 Rising Edge Trigger Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM01FEN : PWM0_CH1 Falling Edge Trigger Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM01PEN : PWM0_CH1 Period Trigger Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PWM01CEN : PWM0_CH1 Center Trigger Enable Bit\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
A/D Trigger Condition for SAMPLE01
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE02
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE03
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE10
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE11
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE12
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLE13
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 6 for SAMPLE06
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 7 for SAMPLE07
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 8 for SAMPLE10
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 9 for SAMPLE11
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 10 for SAMPLE12
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 11 for SAMPLE13
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 12 for SAMPLE14
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 13 for SAMPLE15
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 14 for SAMPLE16
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 15 for SAMPLE17
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 1 for SAMPLE01
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRG7_0 : A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Start an ADC conversion when the priority is given to SAMPLE0x
End of enumeration elements list.
SWTRG15_8 : A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion\n
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : 0
No effect
1 : 1
Start an ADC conversion when the priority is given to SAMPLE1x
End of enumeration elements list.
A/D SAMPLE Module Software Start Register
address_offset : 0x48 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
A/D Start of Conversion Pending Flag Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STPF7_0 : A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag\n
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
0 : 0
There is no pending conversion for SAMPLE0x
1 : 1
SAMPLE0x ADC start of conversion is pending
End of enumeration elements list.
STPF15_8 : A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag \n
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : 0
There is no pending conversion for SAMPLE1x
1 : 1
SAMPLE1x ADC start of conversion is pending
End of enumeration elements list.
A/D ADINT3~0 Interrupt Flag Overrun Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOVF7_0 : A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
No SAMPLE0x event overrun
1 : 1
Indicates a new SAMPLE0x event is generated while an old one event is pending
End of enumeration elements list.
SPOVF15_8 : A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag\n
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : 0
No SAMPLE1x event overrun
1 : 1
Indicates a new SAMPLE1x event is generated while an old one event is pending
End of enumeration elements list.
A/D SAMPLE Module Start of Conversion Overrun Flag Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE00 Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : A/D SAMPLE MODULE 0,1 Channel Selection\n
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
ADCn_CH0
#0001 : 1
ADCn_CH1
#0010 : 2
ADCn_CH2
#0011 : 3
ADCn_CH3
#0100 : 4
ADCn_CH4
#0101 : 5
ADCn_CH5
#0110 : 6
ADCn_CH6
#0111 : 7
ADCn_CH7
#1000 : 8
VBG.\nOP1
#1001 : 9
VTEMP
#1010 : 10
AVSS
#1011 : 11
OP0
End of enumeration elements list.
TRGSEL : A/D SAMPLE MODULE Start Of Conversion Trigger Source Selection\n
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Disable hardware trigger
#0001 : 1
External pin (STADC) trigger
#0010 : 2
ADC ADINT0 interrupt EOC pulse trigger
#0011 : 3
ADC ADINT1 interrupt EOC pulse trigger
#0100 : 4
Timer0 overflow pulse trigger
#0101 : 5
Timer1 overflow pulse trigger
#0110 : 6
Timer2 overflow pulse trigger
#0111 : 7
Timer3 overflow pulse trigger
#1000 : 8
EPWM0_CH0 trigger
#1001 : 9
EPWM0_CH2 trigger
#1010 : 10
EPWM0_CH4 trigger
#1011 : 11
EPWM1_CH0 trigger
#1100 : 12
EPWM1_CH2 trigger
#1101 : 13
EPWM1_CH4 trigger
#1110 : 14
PWM0_CH0 trigger
#1111 : 15
PWM0_CH1 trigger
End of enumeration elements list.
TRGDLYCNT : A/D SAMPLE MODULE Start Of Conversion Trigger Delay Time\n
bits : 8 - 15 (8 bit)
access : read-write
TRGDLYDIV : A/D SAMPLE MODULE Start Of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
ADC_CLK/1
#01 : 1
ADC_CLK/2
#10 : 2
ADC_CLK/4
#11 : 3
ADC_CLK/16
End of enumeration elements list.
EXTREN : A/D External Pin Rising Edge Trigger Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D external pin rising edge trigger Disabled
#1 : 1
A/D external pin rising edge trigger Enabled
End of enumeration elements list.
EXTFEN : A/D External Pin Falling Edge Trigger Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D external pin falling edge trigger Disabled
#1 : 1
A/D external pin falling edge trigger Enabled
End of enumeration elements list.
A/D SAMPLE01 Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE02 Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE03 Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE04 Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIMUSEL0 : A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored. If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL1 : A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored. If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL2 : A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored. If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL3 : A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored. If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL4 : A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored. If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL5 : A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored. if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL6 : A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored. If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
SIMUSEL7 : A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection \n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored. If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal
End of enumeration elements list.
A/D SAMPLE05 Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE06 Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE07 Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE10 Control Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE11 Control Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 2 for SAMPLE02
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE12 Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE13 Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE14 Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE15 Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE16 Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE17 Control Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE Module Simultaneous Sampling Mode Select Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Result Compare Register 0
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : A/D Result Compare Enable Bit\nSet this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE MODULE conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Disabled
#1 : 1
Compare Enabled
End of enumeration elements list.
ADCMPIE : A/D Result Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPSPL : Compare SAMPLE MODULE Selection\n
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared
#001 : 1
SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared
#010 : 2
SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared
#011 : 3
SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared
#100 : 4
SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared
#101 : 5
SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared
#110 : 6
SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared
#111 : 7
SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared
End of enumeration elements list.
CMPMCNT : Compare Match Count\nWhen the specified A/D SAMPLE MODULE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1. When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPDAT : Compared Data\nThe 12 bits data is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write
A/D Result Compare Register 1
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Status Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID7_0 : ADDR07~ ADDR00 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n
bits : 0 - 7 (8 bit)
access : read-only
VALID15_8 : ADDR17~ ADDR10 Data Valid Flag (Read Only)\nIt is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.\n
bits : 8 - 15 (8 bit)
access : read-only
OV7_0 : ADDR07~ ADDR00 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.\n
bits : 16 - 23 (8 bit)
access : read-only
OV15_8 : ADDR17~ADDR10 Overrun Flag (Read Only)\nIt is a mirror to OV bit in SAMPLE 1 A/D result data register EADC_AD0DAT1x.\n
bits : 24 - 31 (8 bit)
access : read-only
A/D Status Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADIF0 : A/D ADINT0 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT0 interrupt pulse received
#1 : 1
ADINT0 interrupt pulse has been received
End of enumeration elements list.
ADIF1 : A/D ADINT1 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT1 interrupt pulse received
#1 : 1
ADINT1 interrupt pulse has been received
End of enumeration elements list.
ADIF2 : A/D ADINT2 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it. \nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
no ADINT2 interrupt pulse received
#1 : 1
ADINT2 interrupt pulse has been received
End of enumeration elements list.
ADIF3 : A/D ADINT3 Interrupt Flag\nNote1: This bit is cleared by writing 1 to it.\nNote2:This bit indicates whether an A/D conversion of specific SAMPLE MODULE has been completed
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT3 interrupt pulse received
#1 : 1
ADINT3 interrupt pulse has been received
End of enumeration elements list.
ADCMPO0 : ADC Compare 0 Output Status
The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE. Software can use it to monitor the external analog input pin voltage status.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting
#1 : 1
Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting
End of enumeration elements list.
ADCMPO1 : ADC Compare 1 Output Status
The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE MODULE. Software can use it to monitor the external analog input pin voltage status.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting
#1 : 1
Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting
End of enumeration elements list.
ADCMPF0 : ADC Compare 0 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet EADC_CMP0 setting
#1 : 1
Conversion result in ADDR meets EADC_CMP0 setting
End of enumeration elements list.
ADCMPF1 : ADC Compare 1 Flag\nWhen the specific SAMPLE MODULE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet EADC_CMP1 setting
#1 : 1
Conversion result in ADDR meets EADC_CMP1 setting
End of enumeration elements list.
BUSY0 : Busy/Idle (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter 0 (ADC0) is in idle state
#1 : 1
A/D converter 0 (ADC0) is doing conversion
End of enumeration elements list.
CHANNEL0 : Current Conversion Channel (Read Only)\n
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
#0000 : 0
ADC0_CH0
#0001 : 1
ADC0_CH1
#0010 : 2
ADC0_CH2
#0011 : 3
ADC0_CH3
#0100 : 4
ADC0_CH4.\nADC0_CH5
#0110 : 6
ADC0_CH6
#0111 : 7
ADC0_CH7
#1000 : 8
VBG
#1001 : 9
VTEMP
#1010 : 10
AVSS
#1011 : 11
OPA0_O
End of enumeration elements list.
BUSY1 : Busy/Idle\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter 1 (ADC1) is in idle state
#1 : 1
A/D converter 1 (ADC1) is doing conversion
End of enumeration elements list.
CHANNEL1 : Current Conversion Channel (Read Only)\n
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
#0000 : 0
ADC1_CH0
#0001 : 1
ADC1_CH1
#0010 : 2
ADC1_CH2
#0011 : 3
ADC1_CH3
#0100 : 4
ADC1_CH4
#0101 : 5
ADC1_CH5
#0110 : 6
ADC1_CH6
#0111 : 7
ADC1_CH7
#1000 : 8
OPA1_O
End of enumeration elements list.
ADOVIF : All A/D Interrupt Flag Overrun Bits Check \nNote: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1
#1 : 1
Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1
End of enumeration elements list.
STOVF : For All A/D SAMPLE MODULE Start Of Conversion Overrun Flags Check\nNote: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE MODULE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1
#1 : 1
Any one of SAMPLE MODULE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1
End of enumeration elements list.
AVALID : For All SAMPLE MODULE A/D Result Data Register ADDR Data Valid Flag Check\nNote: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE MODULE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1
#1 : 1
Any one of SAMPLE MODULE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1
End of enumeration elements list.
AOV : For All SAMPLE MODULE A/D Result Data Register Overrun Flags Check \nNote: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE MODULE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1
#1 : 1
Any one of SAMPLE MODULE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1
End of enumeration elements list.
A/D Timing Control Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTSMPT0 : ADC0 Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
bits : 0 - 7 (8 bit)
access : read-write
EXTSMPT1 : ADC1 Extend Sampling Time
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.
bits : 16 - 23 (8 bit)
access : read-write
A/D Data Register 3 for SAMPLE03
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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