SYS_PDID

SYS_WAKEUP

SYS_RSTDBCNT

SYS_RSTDBEN

SYS_IPRST1

SYS_NMICTL

SYS_RSTSTS

SYS_AHBCTL

SYS_GPA_MFPL

SYS_GPA_MFPH

SYS_GPB_MFPL

SYS_GPB_MFPH

SYS_BOOTSET

SYS_GPC_MFPL

SYS_GPC_MFPH

SYS_GPD_MFPL

SYS_LVMPADDR

SYS_LVMPLEN

SYS_RVMPADDR

SYS_RVMPLEN

SYS_EPADPUEN

SYS_GPADS

SYS_GPAIBE

SYS_GPBIBE

SYS_GPCIBE

SYS_IPRST0

SYS_GPDIBE

SYS_GPDDS

SYS_LVDCTL

PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 23 (24 bit)
access : read-only

I2C0WE : I2C0 Wake-up Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1WE : I2C1 Wake-up Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOWE : GPIO Wake-up Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCWE : RTC Wake-up Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTWE : WDT Wake-up Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0WE : Timer0 Wake-up Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1WE : Timer1 Wake-up Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2WE : Timer2 Wake-up Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3WE : Timer3 Wake-up Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0WE : UART0 Wake-up Enable Control\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1WE : UART1 Wake-up Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2WE : UART2 Wake-up Enable Control\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDWE : USB Device Wake-up Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBHWE : USB Host Wake-up Enable Control\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0WF : I2C0 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1WF : I2C1 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIOWF : GPIO Wake-up Flag\nNote: Write 1 to clear this bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCWF : RTC Wake-up Flag\nNote: Write 1 to clear this bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTWF : WDT Wake-up Flag\nNote: Write 1 to clear this bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0WF : Timer0 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1WF : Timer1 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2WF : Timer2 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3WF : Timer3 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0WF : UART0 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1WF : UART1 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2WF : UART2 Wake-up Flag\nNote: Write 1 to clear this bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDWF : USB Device Wake-up Flag\nNote: Write 1 to clear this bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBHWF : USB Host Wake-up Flag\nNote: Write 1 to clear this bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTDBCNT : External NRESET De-bounce Counter \n
bits : 0 - 15 (16 bit)
access : read-write

RSTDBEN : External NRESET De-bounce Control\nThis bit is to enable or disable the external nRESET pin de-bounce process. \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTFRST : WDT Hardware Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2RST : UART2 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMRST : PWM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1RST : I2C1 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPIMRST : SPIM Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDRST : USB Device Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3RST : Timer3 Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTPRST : WDT Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SRST : I2S Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBHRST : USB Host Controller Reset\nSetting this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDHRST : SDH Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRAMRST : SRAM Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1RST : SPI1 Controller Reset\nSet this bit to 1 will generate a reset signal to the USB host controller. User needs to set this bit to 0 to release from the reset state.\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCIEN : RTC Interrupt NMI Source Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTIEN : WDT Interrupt NMI Source Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORIEN : Power on Interrupt NMI Source Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EINT0IEN : External GPIO Group 0 NMI Source Enable Control \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EINT1IEN : External GPIO Group 1 NMI Source Enable Control \n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EINT2IEN : External GPIO Group 2 NMI Source Enable Control \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EINT3IEN : External GPIO Group 3 NMI Source Enable Control \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDIEN : Low Voltage Detect NMI Source Enable Control \n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCIF : RTC Interrupt Flag (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WDTIF : Watch Dog Timer (WDT) Interrupt Flag (Read Only)\n
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PORIF : Power on Reset (POR) Interrupt Flag (Read Only)\n
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EINT0IF : External GPIO Group 0 Interrupt Flag (Read Only)\n
bits : 19 - 19 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EINT1IF : External GPIO Group 1 Interrupt Flag (Read Only)\n
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EINT2IF : External GPIO Group 2 Interrupt Flag (Read Only)\n
bits : 21 - 21 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EINT3IF : External GPIO Group 3 Interrupt Flag (Read Only)\n
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LVDIF : Low Voltage Detect (LVD) Interrupt Flag (Read Only)\n
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PINRF : Reset Status for External NReset Pin\nNote: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : Reset Status for Low Voltage Reset\nNote: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : Reset Status for Watch Dog Reset\nNote: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : Reset Status for Software Setting\nNote: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORF : Reset Status for POR Reset Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRISEL : AHB Bus Arbitration Mode Control The priority mode for fixed priority mode is I2S SDH USBH USBD SPIM M4(S) M4(D) M4(I)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPUHPRI : Enable Raising the Priority of CPU in IRQ Period\nIt can be used to reduce the interrupt latency in a real-time system. Setting this bit, the CPU will have the highest AHB priority.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRISTS : Interrupt Active Status in CPUHPRI Enabled Mode\nIf it is high, the CPU has the highest AHB bus priority. It is set when the CPUHPRI is enabled and the external IRQ is active. This bit is cleared by writing 1 to it. Therefore, if exiting from the IRQ when CPUHPRI is enabled, PRISTS must be cleared. Otherwise, the CPU always has the highest AHB bus priority.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 28 - 30 (3 bit)
access : read-write

PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 30 (3 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 30 (3 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 30 (3 bit)
access : read-write

BOOTSET : System Mode Configuration\nNote: If BOOTSET is equal to ICE Mode, the software cannot change BOOTSET to other mode. But other modes don't have this limitation.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PC4MFP : PC.4 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PC5MFP : PC.5 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PC6MFP : PC.6 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 30 (3 bit)
access : read-write

PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PC12MFP : PC.12 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

PC13MFP : PC.13 Multi-function Pin Selection
bits : 20 - 22 (3 bit)
access : read-write

PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 26 (3 bit)
access : read-write

PD0MFP : PD.0 Multi-function Pin Selection
bits : 0 - 2 (3 bit)
access : read-write

PD1MFP : PD.1 Multi-function Pin Selection
bits : 4 - 6 (3 bit)
access : read-write

PD2MFP : PD.2 Multi-function Pin Selection
bits : 8 - 10 (3 bit)
access : read-write

PD3MFP : PD.3 Multi-function Pin Selection
bits : 12 - 14 (3 bit)
access : read-write

PD4MFP : PD.4 Multi-function Pin Selection
bits : 16 - 18 (3 bit)
access : read-write

ADDR : Load VECMAP Address Register\nThis is the start address for mapping to the address 0x0000_0000 in VECMAP function. Only when CPU reset or setting RLDVMP to 1, the loading signal will be loaded to the SYS_RVMPADDR register. \nNote: This register can only be reset by CHIPRST and HW Reset.
bits : 0 - 31 (32 bit)
access : read-write

LEN : LD_VECMAP Length\nThis is the memory length loading signal for mapping to the address 0x0000_0000 in VECMAP function. Only when OCPU reset or setting RLDVMP to 1, the loading signal will be loaded to the SYS_RVMPLEN register.\nNote1: The maximum mapping length is 128K bytes\nNote2: This register only can be reset by CHIPRST and HW Reset.
bits : 0 - 7 (8 bit)
access : read-write

ADDR : Real VECMAP Address Register Parameter\nThis is the real start address parameter for mapping to the address 0x0000_0000 in VECMAP function. (Default value is mapping to IBR_ROM start address.)\nNote: This register is only loaded from ADDR during CPU Reset process (SYS_IPRST0[0]) or setting RLDVMP.
bits : 0 - 31 (32 bit)
access : read-only

RLDVMP : Load VECMAP Parameter Signal\nNote: This bit is auto cleared to 0
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEN : Real VECMAP Length\nThis is the real memory length for mapping to the address 0x0000_0000 in VECMAP function. \nNote1: Read Only\nNote2: These bits are only loaded from LEN when setting CPURST (SYS_IPRST0[0]) or setting RLDVMP.
bits : 24 - 31 (8 bit)
access : read-write

EPADPUEN : Embedded SPI Flash Pad Pull-up Enable Control\nNote: In Power-down mode, user should set EPADPUEN[4:0] to 0x12.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0DS : PA.0 Driving Strength Control\nSetting driving strength for PA.0 analog / digital combo pin.\n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA1DS : PA.1 Driving Strength Control\nSetting driving strength for PA.1 analog / digital combo pin.\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA2DS : PA.2 Driving Strength Control\nSetting driving strength for PA.2 analog / digital combo pin.\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA3DS : PA.3 Driving Strength Control\nSetting driving strength for PA.3 analog / digital combo pin.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA4DS : PA.4 Driving Strength Control\nSetting driving strength for PA.4 analog / digital combo pin.\n
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA5DS : PA.5 Driving Strength Control\nSetting driving strength for PA.5 analog / digital combo pin.\n
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA6DS : PA.6 Driving Strength Control\nSetting driving strength for PA.6 analog / digital combo pin.\n
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA7DS : PA.7 Driving Strength Control\nSetting driving strength for PA.7 analog / digital combo pin.\n
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IBSELx : None
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMOSENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINONx : Note1: If setting to 0, the input signal from PAD will always be zero.\nNote2: If using PA.0~PA.7 as analog pads, remember to disable input buffer.
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 24 - 30 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMOSENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 16 - 30 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMOSENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 16 - 30 (15 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : Processor Core One-shot Reset\nSetting this bit will only reset the processor core, and this bit will automatically return to 0 after the 2 clock cycles.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRST : Chip One-shot Reset\nSetting this bit will reset the whole chip, including processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMOSENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IBSELx : None
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SMTENx : Note: If both Schmitt Trigger and CMOS input buffer are set to 0, the input signal from PAD will always be zero.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINONx : Note1: If setting to 0, the input signal from PAD will always be zero.\nNote2: If using PD.2, PD.3, and PD.4 as analog pads, user must disable PD.2, PD.3, and PD.4 input buffer.
bits : 18 - 20 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD2DS : PD.2 Driving Strength Control\nSetting driving strength for PD.2 analog / digital combo pin.\n
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD3DS : PD.3 Driving Strength Control\nSetting driving strength for PD.3 analog / digital combo pin.\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD4DS : PD.4 Driving Strength Control\nSetting driving strength for PD.4 analog / digital combo pin.\n
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDIF : Low Voltage Detect Flag\nNote: This bit is useful when LVDEN is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDSEL : Low Voltage Detection Level Selection\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVDEN : Low Voltage Detection Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVREN : Low Voltage Reset Enable Control\nNote: The voltage threshold level is 2.4V
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORENB : Power on Reset Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.